/******************************************************************************/
// @copyright   Copyright Notification
//   No part may be reproduced except as authorized by written permission.
//   The copyright and the foregoing restriction extend to reproduction in all media.
//   Trademark 2010, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TTA, TTC).
//   All rights reserved.
// @version: IWD_10wk37
// $Date: 2010-09-16 11:37:47 +0200 (Thu, 16 Sep 2010) $
// $Rev: 3920 $
/******************************************************************************/
module InterRat_CellReSelection_EtoU_UTRAN
{
//=========================================================================
// Imports
//=========================================================================

  import from CommonIratDefs all;
  import from UTRAN_RRC_ASN1_Definitions language "ASN.1:1997" all;
  import from UTRAN_ASP_Definitions language "ASN.1:1997" all;
  import from UTRAN_ASN1_Templates all;
  import from UTRAN_Component all;
  import from UTRAN_CellInfo all;
  import from UTRAN_CommonFunctions all;
  import from UTRAN_RAB_Functions all;
  import from UTRAN_Templates all;
  import from UTRAN_TypeDefs all;
  import from UTRAN_ConfigurationSteps all;
  
  //imports needed for function f_UTRAN_TransitToCellPCH
  import from UTRAN_RAB_Templates all;
  import from CommonDefs all;
  import from UTRAN_RAB_TemplatesFDD all;

//==============================================================================
// Templates
//==============================================================================

  template (value) DedicatedPriorityInformation cs_DedPrioInfo ( template (value) PriorityLevelList p_PrioLevelList ) := {
    action_ := {
      configureDedicatedPriorities := {
        t_322 := m5,
        priorityLevelList := p_PrioLevelList,
        eutraDetection := true
      }
    }
  };

  template (value) PriorityLevelList cs_PrioLevelList_TDD ( UARFCN p_UARFCN,
                                                            EARFCN p_EARFCN ) := {
    {
      priority      := 5,
      radioAccessTechnology := {
        utraTDD := {
          { uarfcn := p_UARFCN }
        }
      }
    },
    {
      priority       := 4,
      radioAccessTechnology := {
        eutra := {
          { earfcn := p_EARFCN }
        }
      }
    }
  };

  template (value) PriorityLevelList cs_PrioLevelList_FDD (  UARFCN p_UARFCN,
                                                             EARFCN p_EARFCN  ) := {
    {
      priority         := 5,
      radioAccessTechnology := {
        utraFDD := {
          { uarfcn := p_UARFCN }
        }
      }
    },
    {
      priority          := 4,
      radioAccessTechnology := {
        eutra := {
          { earfcn := p_EARFCN }
        }
      }
    }
  };
 
  template (omit) UE_ConnTimersAndConstants_v860ext cs_UEConnTimersConst_v860ext := { t_323 := omit };
  
  template (value) DedicatedPriorityInformation cs_DedPrioInfo_FDD ( template (value) PriorityLevelList p_PrioLevelList ) := {
    action_ := {
      configureDedicatedPriorities := {
        t_322 := m5,
        priorityLevelList := p_PrioLevelList,
        eutraDetection := true
      }
    }
  };

  template (value) UTRANMobilityInformation_v860ext2_Type cs_UTRANMobilityInformation_v860ext2 ( template (omit) E_RNTI                             p_E_RNTI,
                                                                                                 template (value) UE_ConnTimersAndConstants_v860ext p_UE_ConnTimersAndConstants_v860ext,
                                                                                                 template (omit) DedicatedPriorityInformation       p_DedicatedPriorityInformation ) :=
  {
    utranMobilityInformation_v860ext := {
      newPrimary_E_RNTI            := p_E_RNTI,
      ue_ConnTimersAndConstants    := p_UE_ConnTimersAndConstants_v860ext,
      dedicatedPriorityInformation := p_DedicatedPriorityInformation
    },
    nonCriticalExtensions := omit
  }
  
  template (value) UTRAN_DRX_CycleLengthCoefficient_r7 cs_UTRAN_DRX_CycleLengthCoefficient (UTRAN_DRX_CycleLengthCoefficient_r7.drx_CycleLengthCoefficient p_DRX_CycleLengthCoefficient) := {
    drx_CycleLengthCoefficient := p_DRX_CycleLengthCoefficient,
    drx_CycleLengthCoefficient2 := omit,
    timeForDRXCycle2 := omit
  }

//==============================================================================
// Functions
//==============================================================================

  /*
   * @desc      Function for transistion of UE to CELL_PCH.
   *            Function is according to 34.108 cl. 7.4.2.7.1
   * @status
   */
  function f_UTRAN_TransitToCellPCH ( UTRAN_CellId_Type p_CellId ) runs on UTRAN_PTC {
  
    var UTRAN_CFN_Info_Type v_CfnInfo := f_CalculateActTime (p_CellId);
    var UTRAN_SecurityInfo_Type v_SecurityInfo := f_UTRAN_Security_Get ( );
    var RRC_TransactionIdentifier v_RRC_TI := tsc_RRC_TI;
    
    f_Delay(0.5);//Wait 500ms to allow any outstanding acknowledgements to be received.
    
    //@siclog "Step 1" siclog@
    //Send PHYSICAL CHANNEL RECONFIGURATION message
    U_AM.send ( cas_RLC_Data_Req_NoCnf ( p_CellId,
                                         tsc_RB2,
                                         cs_PhysicalChannelReconfiguration_FDD (v_SecurityInfo.dl_IntegrityCheckInfo,
                                                                                v_RRC_TI,
                                                                                v_CfnInfo.actTime,
                                                                                omit,
                                                                                cell_PCH,
                                                                                cs_UTRAN_DRX_CycleLengthCoefficient(3),
                                                                                tsc_MaxAllowPwr)));

    //Configure CELL_PCH in SS
    //Needed?
    
    //@siclog "Step 2" siclog@
    //Receive PHYSICAL CHANNEL RECONFIGURATION COMPLETE
    U_AM.receive (car_RLC_Data_Ind (p_CellId,
                                    tsc_RB2,
                                    cr_PhysicalChannelReconfigurationComplete(v_RRC_TI)));
    
    f_Delay(0.5);//Wait 500ms to allow any outstanding acknowledgements to be received.
  }

  /*
   * @desc      REFERENCE TS 36.523-1 clause 6.2.3.3
   * @status
   */
  function f_TC_6_2_3_3_UTRAN ( ) runs on UTRAN_PTC {

    var integer v_T1_CPICH_Cell5, v_T1_PCCPCH_Cell5, v_T2_CPICH_Cell5, v_T2_PCCPCH_Cell5, v_T3_CPICH_Cell5, v_T3_PCCPCH_Cell5;
    var boolean v_TriggerRxd := false;
    var IRAT_CoOrd_SysInfo_Type v_EUTRASysInfo;
    var UtraServingCellPriorityValue_Type v_UtraPriorityValue_T0;
    var UtraServingCellPrioritySearch1_Type  v_S_PrioritySearch1_T0;
    var UtraServingCellthreshServingLow_Type v_ThreshServingLow_T0;
    var EutraFrequencyAndPriorityInfoPriorityValue_Type v_EutraPriorityValue_T0, v_EutraPriorityValue_Step5;
    var EutraFrequencyAndPriorityInfoQrxLevMin_Type v_QrxLevMinEutra_T0;
    var EutraFrequencyAndPriorityInfoThreshXhigh_Type v_ThreshXhigh_T0;
    var EutraFrequencyAndPriorityInfoThreshXlow_Type v_ThreshXlow_T0;
    v_T1_CPICH_Cell5 := -90;
    v_T1_PCCPCH_Cell5 := -92;
    v_T2_CPICH_Cell5 := -60;
    v_T2_PCCPCH_Cell5 := -62;
    v_T3_CPICH_Cell5 := -70;
    v_T3_PCCPCH_Cell5 := -72;
    v_UtraPriorityValue_T0 := 4;
    v_S_PrioritySearch1_T0 := 8;
    v_ThreshServingLow_T0 := 4;
    v_EutraPriorityValue_T0 := 3;
    v_EutraPriorityValue_Step5 := 5;
    v_QrxLevMinEutra_T0 := -60;
    v_ThreshXhigh_T0 := 16;
    v_ThreshXlow_T0 := 10;

    //Initialise all cells
    f_UTRAN_Init (EUTRA_UTRAN);//RAC is set to '00'O

    //Send the cell info to the EUTRA component
    f_UTRAN_Send_IR_SysInfoToEUTRA (utran_Cell5);

    //Get Cell Parameters for EUTRA cell
     v_EUTRASysInfo := f_WaitForIRATCoOrd_SysInfo (EUTRA);

    //Update SIB19 of cell 5 according to Table 6.2.3.3.3.3-1
    f_UTRAN_SysInfo_SetSIB19 (utran_Cell5, cs_SIB19_UtraAndOneEutraEntry (cs_Utra_PriorityInfoList_Common ( v_UtraPriorityValue_T0,
                                                                                                            v_S_PrioritySearch1_T0,
                                                                                                            v_ThreshServingLow_T0 ),
                                                                          cs_Eutra_FreqAndPriList_OneEntry_Common ( v_EUTRASysInfo.Eutra[0].Arfcn,
                                                                                                                    omit,
                                                                                                                    v_EutraPriorityValue_T0,
                                                                                                                    v_QrxLevMinEutra_T0,
                                                                                                                    v_ThreshXhigh_T0,
                                                                                                                    v_ThreshXlow_T0,
                                                                                                                    omit,
                                                                                                                    true ) ) );

    //Create and configure Cell 5
    //Cell started switched on with default power level, -60 and max attenuation
    f_SS_CreateCellFACH (utran_Cell5);

    //Start sending System Information
    f_UTRAN_SendDefSysInfo (utran_Cell5);

    //Preamble to ensure USIM is updated with valid TAI and to bring UE to initial state
    f_UTRAN_Preamble (utran_Cell5);

    f_UTRAN_TestBody_Set(true);

    //@siclog "Step 1" siclog@
    //Set cell power level according to T1
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);
    f_UTRAN_SetCellPower(utran_Cell5, v_T1_CPICH_Cell5, v_T1_PCCPCH_Cell5);

    //@siclog "Step 3" siclog@
    //Set cell paramters according to T2
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger (EUTRA);
    f_UTRAN_SetCellPower(utran_Cell5, v_T2_CPICH_Cell5, v_T2_PCCPCH_Cell5);

    //@siclog "Step 4" siclog@
    //The UE reselects Cell5 and camps on Cell5.
    f_UTRAN_IdleMode_RAU (utran_Cell5);

    //@siclog "Step 5 -6" siclog@
    //Change the EUTRA cell priority according to Table 6.2.3.3.3.3-2.
    //Send new SIB19 & notify UE of change in System Information
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);
    f_UTRAN_SysInfoModifySIB19 (utran_Cell5, cs_SIB19_UtraAndOneEutraEntry (cs_Utra_PriorityInfoList_Common ( v_UtraPriorityValue_T0,
                                                                                                              v_S_PrioritySearch1_T0,
                                                                                                              v_ThreshServingLow_T0 ),
                                                                            cs_Eutra_FreqAndPriList_OneEntry_Common ( v_EUTRASysInfo.Eutra[0].Arfcn,
                                                                                                                      omit,
                                                                                                                      v_EutraPriorityValue_Step5,
                                                                                                                      v_QrxLevMinEutra_T0,
                                                                                                                      v_ThreshXhigh_T0,
                                                                                                                      v_ThreshXlow_T0,
                                                                                                                      omit,
                                                                                                                      true ) ) );

    //@siclog "Step 7" siclog@
    //Set cell paramters according to T3
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);
    f_UTRAN_SetCellPower(utran_Cell5, v_T3_CPICH_Cell5, v_T3_PCCPCH_Cell5);

    //Wait for the end of the test case
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger (EUTRA);

    f_UTRAN_TestBody_Set (false);

    //Release UTRAN Cell 5
    f_UTRAN_ReleaseCell (utran_Cell5);
  }
  
  /*
   * @desc      REFERENCE TS 36.523-1 clause 6.2.3.4
   * @status
   */
  function f_TC_6_2_3_4_UTRAN ( ) runs on UTRAN_PTC {
  
    var IRAT_CoOrd_SysInfo_Type v_EUTRASysInfo;
    var boolean v_TriggerRxd := false;
    
    //Initialise all cells
    f_UTRAN_Init (EUTRA_UTRAN);
    
    //Send System Information of UTRAN cell to EUTRA component
    f_UTRAN_Send_IR_SysInfoToEUTRA (utran_Cell5);
    
    //Receive the system information of EUTRA cell
    v_EUTRASysInfo := f_WaitForIRATCoOrd_SysInfo (EUTRA);
    
    //Create and configure Cell 5 (cell started switched on but with max attenuation)
    f_SS_CreateCellDCH (utran_Cell5);
    
    //Start sending System Information
    f_UTRAN_SendDefSysInfo (utran_Cell5);
    
    //Bring UE to initial state
    //Bring UE to Idle updated state
    f_UTRAN_Preamble(utran_Cell5);
    //Bring UE to state 6-10 with Interactive or background / UL:64 DL: 64 kbps / PS RAB + UL:3.4 DL:3.4 kbps SRBs for DCCH
    f_UTRAN_UE_64kPS_Rb_Est(utran_Cell5);
    //Bring UE to state 6-12
    f_UTRAN_TransitToCellPCH (utran_Cell5);
    
    //Ask EUTRA PTC to set power levels according to Pre-test conditions (i.e. Cell 1 is suitable neighbour E-UTRA cell )
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);
    
    f_UTRAN_TestBody_Set(true);
    
    //@siclog "Step 1" siclog@
    //Set Cell 5 power level according to the row "T1" in table 6.2.3.4.3.2-1
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger(EUTRA);
    f_UTRAN_SetCellPower (utran_Cell5, -70, -72);
    
    f_UTRAN_TestBody_Set(true);

    //Wait till end of test case and release the UTRAN cell
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger(EUTRA);
    f_UTRAN_ReleaseCell (utran_Cell5);
  }

  /*
   * @desc      REFERENCE TS 36.523-1 clause 6.2.3.5
   * @status
   */
  function f_TC_6_2_3_5_UTRAN ( ) runs on UTRAN_PTC {

    var integer v_T1_CPICH_Cell5 := -65;
    var integer v_T1_PCCPCH_Cell5 := -67;

    //Initialise all cells
    f_UTRAN_Init (EUTRA_UTRAN);

    //Create and configure Cell 5 (cell started switched on but with max attenuation)
    f_SS_CreateCellFACH (utran_Cell5);

    //Start sending System Information
    f_UTRAN_SendDefSysInfo (utran_Cell5);

    //Send System Information of UTRAN cell to EUTRA component
    f_UTRAN_Send_IR_SysInfoToEUTRA (utran_Cell5);

    f_UTRAN_TestBody_Set(true);

    //@siclog "Step 1" siclog@
    //Wait for completion of preamble and then set cell parameters according to T1 in Table 6.2.3.5.3.2-1
    f_UTRAN_InterRAT_InitialiseAuthParams();
    f_UTRAN_SetCellPower(utran_Cell5, v_T1_CPICH_Cell5, v_T1_PCCPCH_Cell5);

    //@siclog "Step 2" siclog@
    //Check if UE camps on Cell 5
    f_UTRAN_IdleMode_RAU (utran_Cell5);

    //Tell the EUTRA component that the test case is over
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);

    f_UTRAN_TestBody_Set (false);

    //Switch/Power off UE and release cell
    f_UTRA_Postamble (utran_Cell5, U1_IDLE);
  }

  /*
   * @desc      REFERENCE TS 36.523-1 clause 6.2.3.6
   * @status
   */
  function f_TC_6_2_3_6_UTRAN ( ) runs on UTRAN_PTC {

    var boolean v_TriggerRxd := false;
    var float v_T320 := 300.0;  //5 minutes : TS 34.123-1 Table 6.2.3.13.3.2-3

    timer t_WaitForRRCConnReq := 30.0;
    timer t_T320;

    //Initialise all cells
    f_UTRAN_Init (EUTRA_UTRAN);

    //Send the cell info to the EUTRA component
    f_UTRAN_Send_IR_SysInfoToEUTRA (utran_Cell5);

    //Create and configure Cell 5
    //Cell started switched on with default power level, -60 and max attenuation
    f_SS_CreateCellFACH (utran_Cell5);

    //Start sending System Information
    f_UTRAN_SendDefSysInfo (utran_Cell5);
    
    //Since UE starts in EUTRA wait for EUTRA PTC to send the Auth Params
    f_UTRAN_InterRAT_InitialiseAuthParams();

    //Wait for preamble to finish on EUTRA PTC and then set cell power level according to T0
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger ( EUTRA );
    f_UTRAN_SetCellPower(utran_Cell5, -115, -115);
    f_SendIRATCoOrd ( EUTRA, cms_IRAT_Trigger );

    f_UTRAN_TestBody_Set( true );

    //@siclog "Step 1" siclog@
    //Wait for Step 1 to be executed on EUTRA PTC
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger (EUTRA);

    //@siclog "Step 2" siclog@
    //Set cell power level according to T1
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);
    f_UTRAN_SetCellPower(utran_Cell5, -65, -65);

    //@siclog "Step 3" siclog@
    //Check for no RRC CONNECTIONREQUEST on cell 5
    t_WaitForRRCConnReq.start;
    alt {
      [] U_TM.receive(car_RRC_ConnReq (utran_Cell5,
                                       tsc_RB0,
                                       cdr_RRC_ConnReq_r8OrLater( ? )))
         {
            t_WaitForRRCConnReq.stop;
            f_UTRAN_SetVerdictFailOrInconc(__FILE__, __LINE__, "Test Case 6.2.3.6 Step 3");
         }
      [] t_WaitForRRCConnReq.timeout { }
    }

    //@siclog "Step 4" siclog@
    //Tell EUTRA PTC to go on with step 4
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);

    //@siclog "Step 9" siclog@
    //Perform Idle Mode RAU
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger (EUTRA);
    f_UTRAN_IdleMode_RAU (utran_Cell5);

    //@siclog "Step 10" siclog@
    //Set cell power level according to T2
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);
    f_UTRAN_SetCellPower(utran_Cell5, -115, -115);

    //Step 12: Set cell power level according to T3
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger (EUTRA);
    f_UTRAN_SetCellPower(utran_Cell5, -65, -65);

    //@siclog "Step 13" siclog@
    //Perform Idle Mode RAU
    f_UTRAN_IdleMode_RAU ( utran_Cell5 );

    //@siclog "Step 14" siclog@
    //Set cell power level according to T4
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);
    f_UTRAN_SetCellPower(utran_Cell5, -115, -115);

    //@siclog "Step 16" siclog@
    //Start timer T320 and set cell power level according to T5
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger ( EUTRA );
    t_T320.start ( v_T320 - 0.1* v_T320 );//timer T320 = 5 minutes - 10% tolerance
    f_UTRAN_SetCellPower(utran_Cell5, -65, -65);

    //@siclog "Step 17" siclog@
    t_T320.timeout;

    //@siclog "Step 18" siclog@
    //Perform Idle Mode RAU
    f_UTRAN_IdleMode_RAU ( utran_Cell5 );

    //Tell the EUTRA PTC that test case has ended
    f_SendIRATCoOrd ( EUTRA, cms_IRAT_Trigger );

    f_UTRAN_TestBody_Set( true );

    //Switch/power off UE
    f_UTRA_Postamble ( utran_Cell5, U1_IDLE );
  }

  /*
   * @desc      REFERENCE TS 36.523-1 clause 6.2.3.13
   * @status
   */
  function f_TC_6_2_3_13_UTRAN ( ) runs on UTRAN_PTC {

    var integer v_T0_CPICH_Cell5, v_T0_PCCPCH_Cell5, v_T1_CPICH_Cell5, v_T1_PCCPCH_Cell5, v_T2_CPICH_Cell5, v_T2_PCCPCH_Cell5;
    var UtraServingCellPriorityValue_Type v_UtraPriorityValue_T0;
    var UtraServingCellPrioritySearch1_Type  v_S_PrioritySearch1_T0;
    var UtraServingCellthreshServingLow_Type v_ThreshServingLow_T0;
    var EutraFrequencyAndPriorityInfoPriorityValue_Type v_EutraPriorityValue_T0;
    var EutraFrequencyAndPriorityInfoQrxLevMin_Type v_QrxLevMinEutra_T0;
    var EutraFrequencyAndPriorityInfoThreshXhigh_Type v_ThreshXhigh_T0;
    var EutraFrequencyAndPriorityInfoThreshXlow_Type v_ThreshXlow_T0;
    var IRAT_CoOrd_SysInfo_Type v_EUTRASysInfo;
    var UTRAN_SecurityInfo_Type v_SecurityInfo;
    var U_RNTI v_U_RNTI;
    var C_RNTI v_C_RNTI;
    var octetstring v_LAC;
    var DRX_CycleLengthStructure v_DRX_CycleLengthStructure;
    var PLMN_Identity v_PLMN_Identity;
    var template (value) DedicatedPriorityInformation v_DedPrioInfo;
    var UTRAN_FDD_TDD v_FDD_TDD_Mode;
    var octetstring v_DomainSpecificNAS_Info;
    var boolean v_TriggerRxd := false;
    var RRC_TransactionIdentifier v_RRC_TI := tsc_RRC_TI;
    var float v_T322 := 300.0;  // 5 minutes : TS 34.123-1 Table 6.2.3.13.3.2-3
    timer t_T322;

    v_UtraPriorityValue_T0 := 3;
    v_S_PrioritySearch1_T0 := 8;
    v_ThreshServingLow_T0 := 4;
    v_EutraPriorityValue_T0 := 4;
    v_QrxLevMinEutra_T0 := -53;
    v_ThreshXhigh_T0 := 16;
    v_ThreshXlow_T0 := 10;
    v_T0_CPICH_Cell5 := -60;
    v_T0_PCCPCH_Cell5 := -62;       // TDD: To be clarified in prose
    v_T1_CPICH_Cell5 := -75;
    v_T1_PCCPCH_Cell5 := -77;       // TDD: To be clarified in prose
    v_T2_CPICH_Cell5 := -60;
    v_T2_PCCPCH_Cell5 := -62;       // TDD: To be clarified in prose

    //Initialise all cells
    f_UTRAN_Init (EUTRA_UTRAN);
    
    //Get FDD or TDD mode
    v_FDD_TDD_Mode := f_UTRAN_CellInfo_GetFDD_TDD (utran_Cell5);
    
    //Send the cell info to the EUTRA component
    f_UTRAN_Send_IR_SysInfoToEUTRA (utran_Cell5);

    //Get Cell Parameters for EUTRA cell
     v_EUTRASysInfo := f_WaitForIRATCoOrd_SysInfo (EUTRA);

    //Update SIB19 of cell 5 according to Table 6.2.3.13.3.3-3
    f_UTRAN_SysInfo_SetSIB19 (utran_Cell5, cs_SIB19_UtraAndOneEutraEntry (cs_Utra_PriorityInfoList_Common ( v_UtraPriorityValue_T0,
                                                                                                            v_S_PrioritySearch1_T0,
                                                                                                            v_ThreshServingLow_T0 ),
                                                                          cs_Eutra_FreqAndPriList_OneEntry_Common ( v_EUTRASysInfo.Eutra[0].Arfcn,
                                                                                                                    omit,
                                                                                                                    v_EutraPriorityValue_T0,
                                                                                                                    v_QrxLevMinEutra_T0,
                                                                                                                    v_ThreshXhigh_T0,
                                                                                                                    v_ThreshXlow_T0,
                                                                                                                    omit,
                                                                                                                    true ) ) );

    //Create and configure Cell 5
    //Cell started switched on with default power level, -60 and max attenuation
    f_SS_CreateCellDCH (utran_Cell5);

    //Start sending System Information
    f_UTRAN_SendDefSysInfo (utran_Cell5);

    //Bring UE to initial state
    f_UTRAN_Preamble (utran_Cell5);
    //Interactive or background / UL:64 DL: 64 kbps / PS RAB + UL:3.4 DL:3.4 kbps SRBs for DCCH
    f_UTRAN_UE_64kPS_Rb_Est(utran_Cell5);
    
    //Notify E-UTRA after setting executing Preamble
    f_SendIRATCoOrd (EUTRA, cms_IRAT_Trigger);

    //Set cell power level according to T0
    f_UTRAN_SetCellPower(utran_Cell5, v_T0_CPICH_Cell5, v_T0_PCCPCH_Cell5);

    f_UTRAN_TestBody_Set(true);

    v_SecurityInfo := f_UTRAN_Security_Get ();
    v_U_RNTI := f_UTRAN_CellInfo_GetU_RNTI (utran_Cell5);
    v_C_RNTI := f_UTRAN_CellInfo_GetC_RNTI(utran_Cell5);
    v_DRX_CycleLengthStructure := f_UTRAN_CellInfo_GetDRX_CycleLength (utran_Cell5);
    v_DomainSpecificNAS_Info := f_UTRAN_CellInfo_GetRAC(utran_Cell5) & f_UTRAN_CellInfo_GetNMO(utran_Cell5);
    v_PLMN_Identity := f_UTRAN_CellInfo_GetPLMNIdentity (utran_Cell5);
    v_LAC := f_UTRAN_CellInfo_GetLAC (utran_Cell5);
    
    //Wait for E-UTRA to set power to T0
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger (EUTRA);
    
    //@siclog "Step 1" siclog@
    //SS sends UTRAN MOBILITY INFORMATION providing dedicated priority information and validity timer to the UE
    if (v_FDD_TDD_Mode == UTRAN_FDD) {
      v_DedPrioInfo := cs_DedPrioInfo (cs_PrioLevelList_FDD (f_UTRAN_CellInfo_GetUARFCN (utran_Cell5),
                                                             v_EUTRASysInfo.Eutra[0].Arfcn));
    }
    else {
      v_DedPrioInfo := cs_DedPrioInfo (cs_PrioLevelList_TDD (f_UTRAN_CellInfo_GetUARFCN (utran_Cell5),
                                                             v_EUTRASysInfo.Eutra[0].Arfcn));
    }
    U_AM.send ( cas_RLC_Data_Req_NoCnf (utran_Cell5,
                                        tsc_RB2,
                                        cs_RRC_UtranMobilityInfo(v_SecurityInfo.dl_IntegrityCheckInfo,
                                                                 v_RRC_TI,
                                                                 omit,
                                                                 omit,
                                                                 v_U_RNTI,
                                                                 v_C_RNTI,
                                                                 omit,
                                                                 cs_UEConnTimersConst,
                                                                 cs_CNInfo( v_PLMN_Identity, v_LAC, v_DRX_CycleLengthStructure, v_DomainSpecificNAS_Info),
                                                                 omit,
                                                                 omit,
                                                                 omit,
                                                                 omit,
                                                                 omit,
                                                                 cs_UTRANMobilityInformation_v860ext2(omit, cs_UEConnTimersConst_v860ext, v_DedPrioInfo))));
                                                                                            
    //Start timer T322 = 5 minutes + 10% tolerance - TS 36.508 cl. 6.7
    t_T322.start ( v_T322 + 0.1* v_T322 );
    
    //@siclog "Step 2" siclog@
    //SS receives the UTRAN MOBILITY INFOMRATION CONFIRM message
    U_AM.receive ( car_RLC_Data_Ind ( utran_CellDedicated,
                                      tsc_RB2,
                                      cr_108_UTRAN_MobilityInfoCnf ( v_RRC_TI ) ) );

    
    //@siclog "Step 3 -6" siclog@
    //The SS releases the UE connection & receives release complete message(s).
    f_UTRAN_RRC_ConnRel ( utran_Cell5, cell_Dch );
    
    //Notify EUTRA after Steps 1 to 6
    f_SendIRATCoOrd ( EUTRA, cms_IRAT_Trigger );
    
    //@siclog "Step 7" siclog@
    //Set cell power level according to T1
    f_UTRAN_SetCellPower(utran_Cell5, v_T1_CPICH_Cell5, v_T1_PCCPCH_Cell5);

    //Wait for EUTRA TAU
    v_TriggerRxd := f_WaitForIRATCoOrd_Trigger ( EUTRA );
    
    //@siclog "Step 11" siclog@
    //Set cell paramters according to T2
    f_UTRAN_SetCellPower(utran_Cell5, v_T2_CPICH_Cell5, v_T2_PCCPCH_Cell5);
    
    //@siclog "Step 12" siclog@
    //The UE reselects Cell5 and camps on Cell5.
    f_UTRAN_IdleMode_RAU ( utran_Cell5, cell_Dch );

    f_UTRAN_TestBody_Set ( false );

    //Notify end of test case
    f_SendIRATCoOrd ( EUTRA, cms_IRAT_Trigger );
    
    //Perform Switch/Power off and Release UTRAN Cell 5
    f_UTRA_Postamble ( utran_Cell5, U1_IDLE );
  }
}
