/******************************************************************************/
// @copyright   Copyright Notification
//   No part may be reproduced except as authorized by written permission.
//   The copyright and the foregoing restriction extend to reproduction in all media.
//   Trademark 2010, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TTA, TTC).
//   All rights reserved.
// @version: IWD_10wk37
// $Date: 2010-09-17 11:39:57 +0200 (Fri, 17 Sep 2010) $
// $Rev: 3955 $
/******************************************************************************/
module MAC_714 {
  //=========================================================================
  // Import Part
  //=========================================================================

  import from EUTRA_CellInfo all;
  import from EUTRA_ConfigurationSteps all;
  import from EUTRA_RRCSteps all;
  import from EUTRA_CommonProcedures all;
  import from EUTRA_LoopBack all;
  import from EUTRA_ASP_TypeDefs all;
  import from EUTRA_AspCommon_Templates all;
  import from EUTRA_CommonDefs all;
  import from EUTRA_CellCfg_Templates all;
  import from EUTRA_RRC_Templates all;
  import from EUTRA_ASP_DrbDefs all;
  import from EUTRA_SRB_Templates all;
  import from EUTRA_Component all;
  import from MAC_Templates all;
  import from L2_CommonTemplates all;
  import from MAC_Functions all;
  import from L2_CommonFunctions all;
  import from EUTRA_RRC_ASN1_Definitions language "ASN.1:1997" all;
  import from EUTRA_SecuritySteps all;
  import from EUTRA_Timing all;
  //import from EUTRA_CapabilityFunctions all;
  import from EUTRA_DRB_Templates all;
  
  //=========================================================================
  // Test case main functions
  //=========================================================================

  // Functions for Test cases
  //==========================================================
  // L2/MAC/7.1
  //==========================================================
  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.1
   * @status    APPROVED
   */
  function f_TC_7_1_4_1_EUTRA() runs on EUTRA_PTC
  { /* Correct handling of UL assignment / dynamic case */
    /* @sic R5s100016 sic@ */

    var C_RNTI v_C_RNTI ;
    var SubFrameTiming_Type v_Timing;
    var SystemFrameNumber_Type v_CurrentFrameNum;
    var SystemFrameNumber_Type v_ExpectedFrameNum;
    var SystemFrameNumber_Type v_FrameNumNewCRNTI;
    var EUTRA_FDD_TDD_Mode_Type  v_EUTRA_FDD_TDD_Mode;
    // determine RAT to make the timing correct later on
    
    timer t_Watchdog := 5.0;

    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    v_EUTRA_FDD_TDD_Mode := f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    f_EUTRA_Preamble(eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    // creates cell and performs registration
    f_EUTRA_LoopBackActivation_State4_DSR_TransMax(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    // Go to state 4 to return no data in UL
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    //@siclog "Step 1" siclog@
    // To stop UL Grant Transmision
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1, cs_TimingInfo_Now);
    // store cell info parameters for C-RNTI
    v_C_RNTI := f_EUTRA_CellInfo_GetC_RNTI(eutra_Cell1);

    v_Timing :=  f_EUTRA_GetNextSendOccasion(eutra_Cell1);      // >100ms in advance; Subframe.Number = 0
    v_CurrentFrameNum := v_Timing.SFN.Number;
    v_FrameNumNewCRNTI := (v_CurrentFrameNum + 4) mod 1024;
    v_ExpectedFrameNum := (v_CurrentFrameNum + 5) mod 1024;

    //R5-095075
    //@siclog "Step 2" siclog@
    DRB.send (cas_DRB_COMMON_REQ_PDCP_SDU (eutra_Cell1, tsc_RbId_DRB1, cs_TimingInfo(v_CurrentFrameNum, 0), cs_PDCP_SDUList_1 (crs_PDCP_SDU_16B)));
    //@siclog "Step 3 void" siclog@
    //@siclog "Steps 4 - 6" siclog@
    // preconfig SS to apply different C-RNTI in future
    f_SS_ConfigActiveCellInfo(eutra_Cell1, cs_TimingInfo(v_CurrentFrameNum, 9), cs_NewC_RNTI_ConfigReq(tsc_C_RNTI_Def2));
    // To configure SS to use a different C-RNTI that available at UE
    f_SS_ConfigActiveCellInfo(eutra_Cell1, cs_TimingInfo(v_FrameNumNewCRNTI, 9), cs_NewC_RNTI_ConfigReq(v_C_RNTI));
    // config SS for periodic grant transmission
    if (v_EUTRA_FDD_TDD_Mode == TDD)
      {
        f_EUTRA_PeriodicCyclicULGrantTransmission(eutra_Cell1, cs_TimingInfo(v_CurrentFrameNum, 9), 5, 6, 1, 17);
        
      }
    else
      {
        f_EUTRA_PeriodicCyclicULGrantTransmission(eutra_Cell1, cs_TimingInfo(v_CurrentFrameNum, 9), 5, 6, 1, 41);
        
      }
    // sub frame 9 implicates for FDD and default UL/DL combination for TDD, the dat is received in Sub Frame 3
    // Imcs =5, Nprb=6, Grant period =1 Sub frame and num of cycles =41 for FDD and 17 for TDD spanning over 40 ms C-RNTI
    // The PDCP SDU =16 bytes, 2 bytes PDCP header, 2 bytes RLC header, 2 bytes MAC header. Total 22 bytes =176 bits.
    // The TBS selelcted in 504 Imcs =1, Nprb=7), the excess  bytes can be utilised for any RLC status PDU or MAC control elements triggered or [MAC padding.
    // the 41 cycles will result in 40 grants with invalid C-RNTI and 1 grants with valid C-RNTI
    // this should result in UL data transmission on FN :=v_Timing.SFN.Number + 5 mod 1024 and sub frame = 3

    //@siclog "Steps 5 - 7" siclog@
    t_Watchdog.start;
    DRB.receive (car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell1,
                                                  tsc_RbId_DRB1,
                                                  cr_TimingInfo(v_ExpectedFrameNum, 3),
                                                  cr_PDCP_SDUList_1(crs_PDCP_SDU_16B)));
    f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 7");
    t_Watchdog.stop;
    
    //test body ends
    f_EUTRA_TestBody_Set(false);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // configure SS for default grant allocation
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);

    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@

    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
  };


  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.4
   * @status    APPROVED
   */
  function f_TC_7_1_4_4_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
       7.1.4.4 : Correct Handling of MAC control information [ Scheduling Requests/ PUCCH]
    */
    var SubFrameTiming_Type v_Timing, v_ExpectedTiming, v_Timing2;
    var SYSTEM_IND v_ReceivedSYSIND;
    var EUTRA_FDD_TDD_Mode_Type  v_EUTRA_FDD_TDD_Mode;
    
    var integer j := 0;
    
    timer t_Watchdog := 5.0;
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    ///////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    v_EUTRA_FDD_TDD_Mode := f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    f_EUTRA_Preamble(eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    // creates cell and performs registration
    //@sic R5-100136
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    f_EUTRA_LoopBackActivation_State4_DSR_TransMax(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    /*f_EUTRA_LoopBackActivation_State4_Generic(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling, 1, 0,
      { cs_508_EPS_QoS_Dedicated_1},
      { cs_508_Tft_Dedicated_1}); //R5-095125 */
    
    // Go to state 4 to return no data in UL
    // to configure SS to report reception of SR
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    ///////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    // to stop UL Grant Transmision
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1, cs_TimingInfo_Now);
    
    //@siclog "Step 1" siclog@
    DRB.send (cas_DRB_COMMON_REQ_PDCP_SDU (eutra_Cell1, tsc_RbId_DRB1, cs_TimingInfo_Now, cs_PDCP_SDUList_10Def));
    
    //@siclog "Step 2" siclog@
    //R5-095125
    //just to avoid v_ExpectedTiming warning for being not initialized
    v_ExpectedTiming.SFN.Number := 0;
    v_ExpectedTiming.Subframe:= {Any := true};
    t_Watchdog.start;// watch dog timer to receive 3 SR's and loop backed PDU
    alt {
      [j==0] SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?)) -> value v_ReceivedSYSIND
        {
          v_Timing := v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          v_ExpectedTiming := f_EUTRA_TimingInfoAdd (v_Timing, 20);
          // Note 36.508 Table 4.6.3-20: sr-ConfigIndex = 30. I.e. periodicity = 20ms as per table 10.1.5 of 36.213
          v_Timing2 := f_EUTRA_TimingInfoAdd (v_Timing, 100); // 100 ms in future schedule the UL grant;
          // this should give sufficient time for UE to send 3 times SR
          //@siclog "Step 3" siclog@
          // Pre config SS for grant transmission
          f_EUTRA_OneULGrantTransmission(eutra_Cell1, cs_TimingInfo(v_Timing2.SFN.Number, 9), 7, 15);// Nprb =15, Imcs=Itbs=7 => TBsize of 1800, sufficiently large for 10 PDU's
          // this guarantees both for FDD and TDD [defaul UL/DL configuration of 1] the UL Data is received in sub frame 3.
          v_Timing2.SFN.Number := (v_Timing2.SFN.Number + 1) mod 1024; // now contains the expected timing of loop backed data
          j := j+1;
          repeat;
        }
      
      [(j>0) and (j < 6)] SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1,
                                                                  cr_TimingInfo(v_ExpectedTiming.SFN.Number, v_ExpectedTiming.Subframe.Number))) -> value v_ReceivedSYSIND
        {
          v_Timing := v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          v_ExpectedTiming := f_EUTRA_TimingInfoAdd (v_Timing, 20);
          // Note 36.508 Table 4.6.3-20: sr-ConfigIndex = 30. I.e. periodicity = 20ms as per table 10.1.5 of 36.213
          
          j := j+1;
          
          if (j==6){
            f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 2: received 6 times SR");
          }
          else{
            repeat;
          }
        }
    };
    
    //@siclog "Step 4" siclog@
    // Received hence end
    DRB.receive(car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell1, tsc_RbId_DRB1, cr_TimingInfo(v_Timing2.SFN.Number, 3), cr_PDCP_SDUList_10Def));
    f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 4");
    t_Watchdog.stop;
    
    //@siclog "Step 5" siclog@
    //R5-095125
    //@sic R5-100136
    t_Watchdog.start(1.00); // 1 second watch dog timer
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 5: UE is still sending scheduling Request during step 5");
        }
      []t_Watchdog.timeout
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 5: UE is not sending any SR in step 5");
        }
      
    };
    
    //test body ends
    f_EUTRA_TestBody_Set(false);
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    ///////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    // to start default grant allocation to UE.
    // to configure SS to stop report reception of SR
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);

    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@

    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
    
  };
  
  
  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.5
   * @status    APPROVED
   */
  function f_TC_7_1_4_5_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
       7.1.4.5 : Correct Handling of MAC control information [ Scheduling Requests/Random Access Procedure]
    */
    var octetstring v_EncodedRlcPdu;
    var octetstring v_EncodedPdcpPdu;
    var C_RNTI v_C_RNTI;
    var SubFrameTiming_Type v_Timing;
    var SYSTEM_IND v_ReceivedSYSIND;
    var DRB_COMMON_IND v_DRB_COMMON_IND;
    var EUTRA_FDD_TDD_Mode_Type  v_EUTRA_FDD_TDD_Mode ;
    var integer v_SR_Count := 0;
    var template (value) PhysicalConfigDedicated v_PhysicalConfigDedicated;
    var template (value) EUTRA_FDD_TDD_CellInfo_Type v_EUTRA_FDD_TDD_Info ; //@sic R5s090312 sic@
    var SR_PUCCH_ResourceIndex_Type v_Sr_PUCCH_ResourceIndex;
    var Dl_Bandwidth_Type v_DlBandwidth; //@sic R5s100073
     var integer v_RBAllocation := 75; // for 5 MHz// @sic R5s100279 sic@
    var template (value) PhysicalConfigDedicated_AntennaInfo_Type v_AntennaInfo;
    var SR_ConfigIndex_Type v_SR_ConfigIndex ; //@sic R5-102177 sic@
    //var template (value) EUTRA_FDD_TDD_CellInfo_Type v_EUTRA_FDD_TDD_CellInfo ;
    //var SR_PUCCH_ResourceIndex_Type v_Sr_PUCCH_ResourceIndex ;
    //var template (value) PhysicalConfigDedicated_AntennaInfo_Type ;
    //var SR_ConfigIndex_Type v_SR_ConfigIndex  ;
    timer t_Watchdog := 5.0;

    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    v_EUTRA_FDD_TDD_Mode := f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
   v_DlBandwidth := f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1);//@sic R5s100073
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    f_EUTRA_Preamble(eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    // creates cell and performs registration
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm

    // Go to state 4 to return data in UL with no scaling
    v_EUTRA_FDD_TDD_Info := f_EUTRA_CellInfo_GetFDD_TDD_Info (eutra_Cell1); //Get FDD or TDD mode from Cell-configuration
    v_Sr_PUCCH_ResourceIndex := f_EUTRA_CellInfo_GetSR_PUCCH_ResourceIndex(eutra_Cell1);
    v_AntennaInfo := f_EUTRA_CellInfo_GetAntennaInfoDedicated (eutra_Cell1);
    v_SR_ConfigIndex := f_EUTRA_CellInfo_GetSR_ConfigIndex (eutra_Cell1 ); //@sic R5-102177 sic@
    //@sic R5s090312 sic@
    v_PhysicalConfigDedicated := cds_PhysicalConfigDedicated_Dsr_TransMax(v_EUTRA_FDD_TDD_Info.cqi_ReportConfig,
                                                                          v_EUTRA_FDD_TDD_Info.soundingRS_UL_Config,
                                                                          v_AntennaInfo,
                                                                          v_Sr_PUCCH_ResourceIndex,
                                                                          v_SR_ConfigIndex
                                                                          );//@sic R5-102177 sic@
    f_EUTRA_GenericRbEst_Common(eutra_Cell1, 0, 0, {cs_508_DRB_ToAddMod_AM_NoStatusRep(tsc_DRB1)}, omit, v_PhysicalConfigDedicated, omit, omit);
    //@sic R5-103816 PDCP Status report made as false sic@
    f_EUTRA_CloseUE_TestLoopModeA(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NoHeaderManipulationDLOnly);

    // to configure SS to report reception of Scheduling Request
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);

    // to configure SS to report reception of C-RNTI MAC Control element in UL PDU
    f_SS_ConfigC_RNTI_IndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);

    // Preconfigures SS for RACH response for RAR and contention resolution
    f_EUTRA_SS_ConfigRachProcedure(eutra_Cell1, omit, cs_RachProcedureConfig_CRNTI(f_EUTRA_CellInfo_GetRAR_TA(eutra_Cell1),
                                                                                   f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1),
                                                                                   0,15 // Imcs= 15 => Itbs=14, Nprb =1 => Grant =256 bits
                                                                                   ));// @sic R5-103846 R5s100522 sic@

    // Configure SS to enable report of PRACH preamble reception
    f_EUTRA_SS_ConfigRachPreambleIndMode (eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    v_C_RNTI := f_EUTRA_CellInfo_GetC_RNTI(eutra_Cell1);
    //test body starts
    // stop UL Default Grant Transmission
    f_EUTRA_StopULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    //@siclog "Step 1" siclog@
    //sic@ R5-105007  remove explicit timing info sic@
    //v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1); // at least 100 ms in future
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_TimingAdvance_0)));

    // 21B PDCP SDU + 2B PDCP H + 2B RLC H+ 1B MacSH  = 26B =208 bits
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_21B)));
    v_EncodedRlcPdu := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    //R5-095078
    //@siclog "Step 1A" siclog@
    //sic@ R5-105007  remove explicit timing info sic@
    //v_Timing.SFN.Number := v_Timing.SFN.Number + 71; // atleast 710 ms in future, 40 ms less than time alignment timer = 750 sub frame
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_1RLCPDU_TA0_NoPad(tsc_LchId_DRB1, v_EncodedRlcPdu))));

    //@siclog "Step 2" siclog@
    t_Watchdog.start;
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, cr_TimingInfo_Any))
        {
          v_SR_Count:= v_SR_Count+1;
          repeat;
        }
      []SYSIND.receive(car_PRACH_Preamble_IND_Any (eutra_Cell1,?))
        {
          t_Watchdog.stop;
          if (v_SR_Count < 64)
          {
            f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 2");
          }
          else
            {
              f_EUTRA_SetVerdictInconc(__FILE__, __LINE__, "Step 2: TP 1 is not tested as UE has sent Scheduling Request dsr-TransMax times");
            }
        }
    };
    //@siclog "Step 3" siclog@
    // Taken care of due to SS preconfiguration
    //@siclog "Step 4" siclog@
    t_Watchdog.start;
    alt {
      []DRB.receive(car_DRB_COMMON_IND_RLC_PDUList (eutra_Cell1,
                                                    tsc_RbId_DRB1,
                                                    cr_TimingInfo_Any,
                                                    { cr_RLC_AMD_1PDU(?, int2bit(0, 10), v_EncodedPdcpPdu) })) -> value v_DRB_COMMON_IND
        // RLC PDU received first
        {
          v_Timing := v_DRB_COMMON_IND.Common.TimingInfo.SubFrame;
          SYSIND.receive (car_C_RNTI_MAC_CntrlElem_IND (eutra_Cell1,
                                                        cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                        v_C_RNTI));
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 4");
          t_Watchdog.stop;
        };
      []SYSIND.receive (car_C_RNTI_MAC_CntrlElem_IND (eutra_Cell1, cr_TimingInfo_Any, v_C_RNTI)) -> value v_ReceivedSYSIND
        // C_RNTI indicator received first
        {
          v_Timing := v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          DRB.receive(car_DRB_COMMON_IND_RLC_PDUList (eutra_Cell1,
                                                      tsc_RbId_DRB1,
                                                      cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                      { cr_RLC_AMD_1PDU( ?, int2bit(0, 10), v_EncodedPdcpPdu) }));
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 4");
          t_Watchdog.stop;
        };
    };
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 1);
    //@siclog "Step 5" siclog@
    // Automatically taken care of
    // to configure SS to stop report reception of C-RNTI MAC Control element in UL PDU

    //@siclog "Steps 5A1 - 5A2 - 5A3 - 5A4" siclog@
    // Preconfigures SS for RACH response for RAR and contention resolution
    f_EUTRA_SS_ConfigRachProcedure(eutra_Cell1, omit,
                                   cs_RachProcedureConfig_CRNTI(f_EUTRA_CellInfo_GetRAR_TA(eutra_Cell1),
                                                                v_DlBandwidth) );// @sic R5-103846  sic@
    // Results in 56 bits grant in RAR the default value for parameter
    // allow UL default grant transmission on SR reception
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1,cs_TimingInfo_Now);
    // to configure SS to stop report reception of SR
    // Note Reception of SR is disabled to avoid race condition between steps 5b and 5d
    f_SS_ConfigSchedulingRequestIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Disable);
    //@siclog "Step 5A" siclog@
    //@sic R5-103872
    v_EUTRA_FDD_TDD_Info := f_EUTRA_CellInfo_GetFDD_TDD_Info ( eutra_Cell1 );
    v_Sr_PUCCH_ResourceIndex := f_EUTRA_CellInfo_GetSR_PUCCH_ResourceIndex ( eutra_Cell1 );
    v_AntennaInfo := f_EUTRA_CellInfo_GetAntennaInfoDedicated (eutra_Cell1);
    v_SR_ConfigIndex := f_EUTRA_CellInfo_GetSR_ConfigIndex (eutra_Cell1 );
    v_PhysicalConfigDedicated := cds_PhysicalConfigDedicated_PUCCH_Resync( v_EUTRA_FDD_TDD_Info.cqi_ReportConfig,
                                                                           v_EUTRA_FDD_TDD_Info.soundingRS_UL_Config,
                                                                           v_AntennaInfo,
                                                                           v_Sr_PUCCH_ResourceIndex,
                                                                           v_SR_ConfigIndex, n8); //@sic R5s100279
    SRB.send ( cas_SRB1_RrcPdu_REQ ( eutra_Cell1,
                                     cs_TimingInfo_Now,
                                     cs_RRCConnectionReconfiguration_RadioResConfig ( tsc_RRC_TI_Def,
                                                                                      cs_RadioResourceConfigDedicated_PhyConfig (v_PhysicalConfigDedicated) ) ) );
    //@sic R5-103872
    alt {
      //@siclog "Step 5A1" siclog@
      []SYSIND.receive(car_PRACH_Preamble_IND_Any (eutra_Cell1,?))
        // UE is executing optional steps 5a1 to 5a4
        {
          //@siclog "Step 5A2" siclog@
          // Automatically taken care of due to SS preconfiguration
          //@siclog "Step 5A3" siclog@
          SYSIND.receive (car_C_RNTI_MAC_CntrlElem_IND (eutra_Cell1,
                                                        cr_TimingInfo_Any,
                                                        v_C_RNTI));
          //@siclog "Step 5A4" siclog@
          // Automatically taken care of due to SS preconfiguration
          SRB.receive ( car_SRB1_RrcPdu_IND ( eutra_Cell1,
                                              cr_508_RRCConnectionReconfigurationComplete ( tsc_RRC_TI_Def ) ) );
          //@siclog "Step 5B" siclog@
          // Not reported to TTCN
          //@siclog "Step 5C" siclog@
          // Automatically taken care of due to SS preconfiguration
          //@siclog "Step 5D" siclog@
        }
      []SRB.receive ( car_SRB1_RrcPdu_IND ( eutra_Cell1,
                                            cr_508_RRCConnectionReconfigurationComplete ( tsc_RRC_TI_Def ) ) )
        {}
        //@siclog "Step 5D" siclog@
        // UE is not executing optional steps 5a1 to 5a4
        //@siclog "Step 5B" siclog@
        // Not reported to TTCN
        //@siclog "Step 5C" siclog@
        // Automatically taken care of due to SS preconfiguration
    } // end of alt statement
    
    //f_SS_ConfigC_RNTI_IndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    //R5-095078
    // to configure SS to start report reception of SR
    f_SS_ConfigSchedulingRequestIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Enable);
   
    //@siclog "Step 10" siclog@
    // Preconfig SS
     select (v_DlBandwidth) {
      case (n50) {  // 10 mhz
        v_RBAllocation := 150;
      }
      case (n100) { // 20 mhz
        v_RBAllocation := 300;
      }
      case else {   // 5 mhz
        v_RBAllocation := 75;
      }
    }
    f_EUTRA_SS_ConfigRachProcedure (eutra_Cell1, omit, cs_RachProcedureConfig_CRNTI(f_EUTRA_CellInfo_GetRAR_TA(eutra_Cell1),
                                                                                    v_DlBandwidth,
                                                                                    v_RBAllocation,4));
    //@siclog "Step 7" siclog@
    // 21B PDCP SDU + 2B PDCP H + 2B RLC H + 1B MAc SH = 26B =208 bits
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_21B)));
    v_EncodedRlcPdu := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu));
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu))));
    
    //@siclog "Step 6" siclog@
    f_EUTRA_StopULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    //@siclog "Step 8" siclog@
    t_Watchdog.start;
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, cr_TimingInfo_Any))-> value v_ReceivedSYSIND
        {
          v_Timing := v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 8");
          v_SR_Count := 7; // 7 more to be received for Both FDD and TDD
          //@sic R5s100279
          // @sic R5s090368 sic@
        }
    };
    //@siclog "Step 8" siclog@
    // Continued
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, cr_TimingInfo_Any))
        {
          v_SR_Count := v_SR_Count - 1;
          if (v_SR_Count > 0)
            {
              repeat;
            }
          else if (v_SR_Count == 0)
            {
              f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 8");  // UE has repeated SR for SR_TRANS_MAX TTI's
            }
        }
      []SYSIND.receive(car_PRACH_Preamble_IND_Any (eutra_Cell1,?))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 8: UE sent  PRACH Preamble, before repeating SR enough number of times ");
          t_Watchdog.stop;
        }
    };
    //@siclog "Step 9" siclog@
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, cr_TimingInfo_Any))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 9: UE continuing to send Scheduling Requests after repeating SR_TRANS_MAX TTI's ");
        }
      []SYSIND.receive(car_PRACH_Preamble_IND_Any (eutra_Cell1, ?))
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 9");
          t_Watchdog.stop;
        }
    };
    //@siclog "Step 10" siclog@
    // Automatically taken care of
    //@siclog "Step 11" siclog@
    // Receive the Loop back Data to end the test case in a cleaned way
    t_Watchdog.start;
    alt {
      []DRB.receive(car_DRB_COMMON_IND_RLC_PDUList (eutra_Cell1,
                                                    tsc_RbId_DRB1,
                                                    cr_TimingInfo_Any,
                                                   { cr_RLC_AMD_1PDU(?, int2bit(1, 10), v_EncodedPdcpPdu) })) -> value v_DRB_COMMON_IND
        // RLC PDU received first
        {
          v_Timing := v_DRB_COMMON_IND.Common.TimingInfo.SubFrame;
          SYSIND.receive (car_C_RNTI_MAC_CntrlElem_IND (eutra_Cell1,
                                                        cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                        v_C_RNTI));
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 11");
          t_Watchdog.stop;
        };
      []SYSIND.receive (car_C_RNTI_MAC_CntrlElem_IND (eutra_Cell1, cr_TimingInfo_Any, v_C_RNTI)) -> value v_ReceivedSYSIND
        // C_RNTI indicator received first
        {
          v_Timing := v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          DRB.receive(car_DRB_COMMON_IND_RLC_PDUList (eutra_Cell1,
                                                      tsc_RbId_DRB1,
                                                      cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                      { cr_RLC_AMD_1PDU(?, int2bit(1, 10), v_EncodedPdcpPdu) }));
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 11");
          t_Watchdog.stop;
        };
    };
    //@siclog "Step 12" siclog@
    //test body ends
    f_EUTRA_TestBody_Set(false);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
   

    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 2);

    //Stop C-RNTI control element reporting
    f_SS_ConfigC_RNTI_IndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    // to configure SS to stop report reception of SR
    f_SS_ConfigSchedulingRequestIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Disable);
    // to configure SS to stop report reception of RACH Preamble
    f_EUTRA_SS_ConfigRachPreambleIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Disable);
        f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1,cs_MAC_TestMode_NormalMode); //@sic R5s100354

    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@

    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
  }; // end of 7.1.4.5


  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.6
   * @status    APPROVED
   */
  function f_TC_7_1_4_6_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
       7.1.4.6 : Correct handling of MAC control information
    */
    var octetstring v_EncodedRlcPdu;
    var octetstring v_EncodedRlcPdu2;
    var octetstring v_EncodedPdcpPdu;
    var octetstring v_EncodedPdcpPdu2;
    var SubFrameTiming_Type v_Timing, v_Timing2;
    var DRB_COMMON_IND v_DRB_COMMON_IND;
    var SYSTEM_IND     v_SYSTEM_IND;

    timer t_Watchdog := 5.0;              // Local wait Timer

    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    // creates cell and performs registration
    f_EUTRA_Preamble (eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // Configure SS to report Scheduling Requests
    f_EUTRA_LoopBackActivation_State4_7146();
    // Configures SS DRB1 in MAC test mode.
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.

    //@siclog "Step 1" siclog@
    // SS ignores scheduling requests and does not allocate any uplink grant
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1, cs_TimingInfo_Now);
    //@siclog "Steps 3 - 7 - 11 - 15" siclog@
    // Preconfig SS for UL Grant of 32 bits
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            0, 2); /* Nprb = 2, Itbs = 0     Table 7.1.7.2.1-1 of 36.213
                                                                      Imcs = 0 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213 */
    //@siclog "Step 2" siclog@
    // 1 MAC PDU = 2 RLC PDU; 1RLC PDU =1 PDCP PDU
    // MAC Header = 1Padding + 2 + 1  = 4B
    // 1 MAC SDU of 12 => RLC SDU= 10, PDCP SDU = 8
    // 1 MAC SDU of 12 => RLC SDU= 10, PDCP SDU = 8
    // Total MAC PDU = 4 + 12 + 12 = 28 B = 224b
    // This is not ideal way to encode to concatenate data at MAC, but is allowed as per core spec.

    v_EncodedPdcpPdu  := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_L8)));
    v_EncodedRlcPdu   := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));

    v_EncodedPdcpPdu2 := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_L8)));
    v_EncodedRlcPdu2  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu2));

    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_2RLCPDU_1Padding_ShortSubHeaders(tsc_LchId_DRB1,
                                                                                                        tsc_LchId_DRB1,
                                                                                                        v_EncodedRlcPdu,
                                                                                                        v_EncodedRlcPdu2))));


    //@siclog "Step 4" siclog@
    //@sic CR raised acc. to CR R2-093439 sic@
    //36.321, section 6.1.2
    t_Watchdog.start;
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?))
        {
          repeat;
        }
      // the padding 2 bytes can be done in 2 allowed ways.
      []DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo_Any,
                                            {cr_MAC_PDU_ShortBSR_2Padding('10'B, ('??1000'B, '?1????'B, '1?????'B, '???11?'B)) })) -> value v_DRB_COMMON_IND
        // received UL MAC PDU(Short BSR (LCGID='2';BS>=6)) @sicCRraised LCGID='3->2'
        // Check BSR value >=6
        {
          f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 4");
          t_Watchdog.stop;
        }
      []DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo_Any,
                                            {cr_MAC_PDU_2Padding_ShortBSR('10'B, ('??1000'B, '?1????'B, '1?????'B, '???11?'B)) })) -> value v_DRB_COMMON_IND
        {
          f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 4");
          t_Watchdog.stop;
        }

    };
    v_Timing := v_DRB_COMMON_IND.Common.TimingInfo.SubFrame;

    //@siclog "Step 5" siclog@
    //wait for Retr-BSR timer expire on UE side = 320SF
    //f_Delay(0.32 - (fl_EUTRA_TimerTolerance (eutra_Cell1, 0.32)));
    
    //@siclog "Steps 5 - 6" siclog@
    // receive SR after Retr-BSR timer expiry
    t_Watchdog.start;
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?))-> value v_SYSTEM_IND;
    v_Timing2 := v_SYSTEM_IND.Common.TimingInfo.SubFrame;
    //@sic R5s100068
    if ((f_EUTRA_SubFrameTimingDuration_Float(v_Timing, v_Timing2) > f_EUTRA_SetTimerToleranceMin(eutra_Cell1, 0.32)) and
        (f_EUTRA_SubFrameTimingDuration_Float(v_Timing, v_Timing2) < f_EUTRA_SetTimerToleranceMax(eutra_Cell1, 0.32)))
      {
        f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 6: UE has sent SR after expiry of Retr-BSR timer");
      }
    else
      {
        f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 6: UE has sent SR before expiry of Retr-BSR timer ");
      };
    
    t_Watchdog.stop;
    
    //@siclog "Step 8" siclog@
    t_Watchdog.start;
    //@sic CR raised acc. to CR R2-093439 sic@
    //36.321, section 6.1.2
    alt {
      // received UL MAC PDU(Short BSR (LCGID='2';BS>=6)) @sicCRraised LCGID='3->2'
      // Check BSR value >=6
      []DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                              tsc_RbId_DRB1,
                                            cr_TimingInfo_Any,
                                            {cr_MAC_PDU_ShortBSR_2Padding('10'B, ('??1000'B, '?1????'B, '1?????'B, '???11?'B))}))
        { }
      []DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo_Any,
                                            {cr_MAC_PDU_2Padding_ShortBSR('10'B, ('??1000'B, '?1????'B, '1?????'B, '???11?'B))}))
        { }
    };
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 8");
    t_Watchdog.stop;
    
    //@siclog "Step 9" siclog@
    // 1 MAC PDU = 1 RLC PDU; 1RLC PDU =1 PDCP PDU
    // MAC Header = 1B
    // 1 MAC SDU of 12 => RLC SDU= 10, PDCP SDU = 8
    // Total MAC PDU = 1 + 12 = 13 B = 104b
    
    v_EncodedPdcpPdu  := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_L8)));
    v_EncodedRlcPdu   := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB2,
                                                                                             v_EncodedRlcPdu))));
    
    //@siclog "Step 10" siclog@
    t_Watchdog.start;
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 10");
    t_Watchdog.stop;
    
    //@siclog "Step 12" siclog@
    t_Watchdog.start;
    //@sic CR raised acc. to CR R2-093439 sic@
    //36.321, section 6.1.2
    alt {
      // received UL MAC PDU (LCGID='2';BS>='8') @sicCRraised LCGID='3->2'
      // Check BSR value >=8
      []DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo_Any,
                                            {cr_MAC_PDU_ShortBSR_2Padding('10'B, ('??1000'B, '?1????'B, '1?????'B))}))
        { }
      []DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo_Any,
                                            {cr_MAC_PDU_2Padding_ShortBSR('10'B, ('??1000'B, '?1????'B, '1?????'B))}))
        { }
    };
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 12");
    t_Watchdog.stop;
    
    //R5-094426
    //@siclog "Step 13" siclog@
    // 1 MAC PDU = 2 RLC PDU; 1RLC PDU =1 PDCP PDU
    // MAC Header = 2 + 1 = 3 B
    // 1 MAC SDU of 6 => RLC SDU= 4, PDCP SDU = 2
    // 1 MAC SDU of 6 => RLC SDU= 4, PDCP SDU = 2
    // Total MAC PDU = 3 + 6 + 6 = 15B = 120b
    v_EncodedPdcpPdu  := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_2B)));
    v_EncodedRlcPdu   := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    v_EncodedPdcpPdu2 := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_2B)));
    v_EncodedRlcPdu2  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu2));

    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_2RLCPDU_ShortSubHeaders(tsc_LchId_DRB3,
                                                                                               tsc_LchId_DRB3,
                                                                                               v_EncodedRlcPdu,
                                                                                               v_EncodedRlcPdu2))));
    //@siclog "Step 14" siclog@
    t_Watchdog.start;
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 14");
    t_Watchdog.stop;

    //@siclog "Step 16" siclog@
    //@sic CR raised (BS#2 -> BS#1;BS#3 -> BS#2) sic@
    t_Watchdog.start;
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cr_TimingInfo_Any,
                                          {cr_MAC_PDU_LongBSR (tsc_BS_0,
                                                               ('?????1'B, '????1?'B, '???1??'B, '??1???'B, '?1????'B, '1?????'B),
                                                               ('??1000'B, '?1????'B, '1?????'B),
                                                               tsc_BS_0)}))-> value v_DRB_COMMON_IND;
     v_Timing := v_DRB_COMMON_IND.Common.TimingInfo.SubFrame;
    // received UL MAC PDU Long BSR (BS#1=>1;BS#2>=8)
    // Check BSRs values >=1 or >=8
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 16");
    t_Watchdog.stop;
    //@sic R5-101179 sic@
    //@siclog "Step 19" siclog@
    // Preconfig SS for UL Grant of 424 bits
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            2, 10); /* Nprb = 10, Itbs = 2     Table 7.1.7.2.1-1 of 36.213
                                                                      Imcs = 2 -> Itbs = 2   MCS index of table 8.6.1-1 of 36.213 */
    //@siclog "Steps 17 - 18" siclog@
    // receive SR after Retr-BSR timer expiry
    t_Watchdog.start;
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?))-> value v_SYSTEM_IND;
    v_Timing2 := v_SYSTEM_IND.Common.TimingInfo.SubFrame;
    if ((f_EUTRA_SubFrameTimingDuration_Float(v_Timing, v_Timing2) > f_EUTRA_SetTimerToleranceMin(eutra_Cell1, 0.32)) and
        (f_EUTRA_SubFrameTimingDuration_Float(v_Timing, v_Timing2) < f_EUTRA_SetTimerToleranceMax(eutra_Cell1, 0.32)))
      {
        f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 18: UE has sent SR after expiry of Retr-BSR timer");
      }
    else
      {
        f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 18: UE has sent SR before expiry of Retr-BSR timer ");
      };
    
    //@siclog "Step 20" siclog@
    alt {
        // order LCH 1, LCH 2 & LCH 3
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_3Subheader_Short_NoPadding(tsc_LchId_DRB1,
                                                                                    int2bit(24,7),
                                                                                    cr_Octet24_Any,
                                                                                    tsc_LchId_DRB2,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB3,
                                                                                    cr_Octet12_Any)}))
        {}
      // order LCH 1, LCH 3 & LCH 2
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_3Subheader_Short_NoPadding(tsc_LchId_DRB1,
                                                                                    int2bit(24,7),
                                                                                    cr_Octet24_Any,
                                                                                    tsc_LchId_DRB3,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB2,
                                                                                    cr_Octet12_Any)}))
        {}
      // order LCH 2, LCH 1 & LCH 3
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_3Subheader_Short_NoPadding(tsc_LchId_DRB2,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB1,
                                                                                    int2bit(24,7),
                                                                                    cr_Octet24_Any,
                                                                                    tsc_LchId_DRB3,
                                                                                    cr_Octet12_Any)}))
        {}
      // order LCH 2, LCH 3 & LCH 1
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_3Subheader_Short_NoPadding(tsc_LchId_DRB2,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB3,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB1,
                                                                                    cr_Octet24_Any)}))
        {}
      // order LCH 3, LCH 1 & LCH 2
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_3Subheader_Short_NoPadding(tsc_LchId_DRB3,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB1,
                                                                                    int2bit(24,7),
                                                                                    cr_Octet24_Any,
                                                                                    tsc_LchId_DRB2,
                                                                                    cr_Octet12_Any)}))
        {}
      // order LCH 3, LCH 2 & LCH 1
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_3Subheader_Short_NoPadding(tsc_LchId_DRB3,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB2,
                                                                                    int2bit(12,7),
                                                                                    cr_Octet12_Any,
                                                                                    tsc_LchId_DRB1,
                                                                                    cr_Octet24_Any)}))
        {}
      [] t_Watchdog.timeout
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 20: UE is not sending MAC PDU ");
        }
    };
    
    t_Watchdog.stop;
    //@sic R5s090377 sic@
    // Transmit RLC status PDU's to bring UE in stable state
    // It is assumed concatenation happens at RLC, hence one RLC PDU is send per Logical channel;
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1,1);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,1);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB3,1);
    
    f_EUTRA_TestBody_Set(false);
    //test body ends
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_OneULGrantTransmission(eutra_Cell1,
                                   cs_TimingInfo_Now,
                                   7, 10); // Itbs = Imcs =7, Nprb = 10 => grant of 1224
    // sufficiently large to receive all loop back PDU's
    
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    // Configure SS to report Scheduling Requests
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB in DL only
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1,cs_MAC_TestMode_NormalMode); //@sic R5s100272
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1,cs_TimingInfo_Now);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@

    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
    
  }; // end of 7.1.4.6

  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.7
   * @status    APPROVED
   */
  function f_TC_7_1_4_7_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
     * 7.1.4.7 : Correct handling of MAC control information */
    var octetstring v_EncodedRlcPdu;
    var octetstring v_EncodedPdcpPdu;
    var SubFrameTiming_Type v_Timing;
    
    timer t_Watchdog := 5.0;              // Local wait Timer
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    f_EUTRA_Preamble (eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // creates cell and performs registration
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    
    f_EUTRA_LoopBackActivation_State4_7147_71413();
    
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    // Configures SS DRB1 in MAC test mode.
    
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    
    //@siclog "Step 1" siclog@
    // SS ignores scheduling requests and does not allocate any uplink grant
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync (eutra_Cell1, cs_TimingInfo_Now);
    
    //100 ms to wait for having an accurate reference to start
    v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1);  // per default 100ms in advance
    v_Timing.Subframe.Number := 0;
    //@siclog "Step 2" siclog@
    // Repeated 2 times
    // 1 MAC PDU = 1 RLC PDU; 1RLC PDU =1 PDCP PDU
    // MAC Header = 1B
    // 1 MAC SDU of 14 => RLC SDU= 12, PDCP SDU = 10
    // Total MAC PDU = 1 + 14  = 15B = 120b (best fit)

    v_EncodedPdcpPdu  := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(int2bit(0, 12), crs_PDCP_SDU_L10)));
    v_EncodedRlcPdu   := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB2, v_EncodedRlcPdu))));
    
    v_Timing.Subframe.Number := 4;// suitable for both FDD and TDD Default
    v_EncodedPdcpPdu  := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(int2bit(1, 12), crs_PDCP_SDU_L10)));
    v_EncodedRlcPdu   := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB2, v_EncodedRlcPdu))));
    
    v_Timing.Subframe.Number := 5;// suitable for both FDD and TDD Default
    //@siclog "Step 3" siclog@
    // 1 MAC PDU = 1 RLC PDU; 1RLC PDU =1 PDCP PDU
    // MAC Header = 1B
    // 1 MAC SDU of 14 => RLC SDU= 12, PDCP SDU = 10
    // Total MAC PDU = 1 + 14  = 15B = 120b
    v_EncodedPdcpPdu  := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_L10)));
    v_EncodedRlcPdu   := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu))));
    //@siclog "Step 5" siclog@
    // Preconfig SS for UL Grant of 32 bits
    v_Timing := f_EUTRA_TimingInfoAdd(v_Timing, 60); //60 ms in future
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                            0, 2); /* Nprb = 2, Itbs = 0          Table 7.1.7.2.1-1 of 36.213
                                                                      Imcs = 0 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213 */
    
    //@siclog "Step 4" siclog@
    /*t_Watchdog.start;
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 4");
    t_Watchdog.stop;*/

    //@siclog "Step 6" siclog@
    t_Watchdog.start;
    DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                         tsc_RbId_DRB1,
                                         cr_TimingInfo_Any,
                                         cr_MAC_PDUList_1 (cr_MAC_PDU_LongBSR(tsc_BS_0, cr_BS_Any, cr_BS_Any, tsc_BS_0))));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 6");
    t_Watchdog.stop;

    //@siclog "Step 7" siclog@
    // UL Grant of 136 bits
    f_EUTRA_OneULGrantTransmission( eutra_Cell1,
                                    cs_TimingInfo_Now,
                                    9, 1); /* Nprb = 1, Itbs = 9          Table 7.1.7.2.1-1 of 36.213
                                              Imcs = 9 -> Itbs = 9   MCS index of table 8.6.1-1 of 36.213 */
    
    //@siclog "Step 8" siclog@
    // Check step
    t_Watchdog.start;
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_1Subheader_TruncatedBSR_RLCPDU(tsc_LchId_DRB2, '01'B, ('?????1'B, '????1?'B, '???1??'B, '??1???'B, '?1????'B, '1?????'B), cr_Octet14_Any)}));
    // received UL MAC PDU Check BSR value >0
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 8");
    t_Watchdog.stop;
    
    // Status PDU to be transmitted for DRB 2
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,1);
    
    //@siclog "Step 10" siclog@
    // Pre config SS for UL Grant of 136 bits
    f_EUTRA_OneULGrantTransmission( eutra_Cell1,
                                    cs_TimingInfo_Now,
                                    9, 1); /* Nprb = 1, Itbs = 9          Table 7.1.7.2.1-1 of 36.213
                                              Imcs = 9 -> Itbs = 9   MCS index of table 8.6.1-1 of 36.213 */
    
    //@siclog "Step 9 void" siclog@
    
    //@siclog "Step 11" siclog@
    // Check step
    t_Watchdog.start;
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_1Subheader_ShortBSR_RLCPDU(tsc_LchId_DRB2, '10'B, ('?????1'B, '????1?'B, '???1??'B, '??1???'B, '?1????'B, '1?????'B), cr_Octet14_Any)}));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 11");
    t_Watchdog.stop;
    
    // Status PDU to be tranmsitted for DRB 1
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,2);
    
    //@siclog "Step 14" siclog@
    // Pre config SS for UL Grant of 152 bits
    f_EUTRA_OneULGrantTransmission( eutra_Cell1,
                                    cs_TimingInfo_Now,
                                    0, 6); /* Nprb = 6, Itbs = 0          Table 7.1.7.2.1-1 of 36.213
                                              Imcs = 0 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213 */
    
    //@siclog "Step 12 void" siclog@
    //@siclog "Step 13 void" siclog@
    
    //@siclog "Step 15" siclog@
    // Check step
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_LongBSR_RLCPDU (tsc_LchId_DRB1, cr_BS_Any, cr_BS_Any, cr_BS_Any, cr_BS_Any, cr_Octet14_Any)}));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 15");
    t_Watchdog.stop;
    
    // Status PDU to be tranmsitted for DRB 1
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 1);
    
    f_EUTRA_TestBody_Set(false);
    //test body ends
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    
    
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB in DL only
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NormalMode); //@sic R5s100272
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@

    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@

  }; // end of 7.1.4.7


  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.8
   * @status    APPROVED
   */
  function f_TC_7_1_4_8_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
     * 7.1.4.8 : Correct Handling of MAC control information [Buffer Status/ Periodic BSR Timer expires] */
    var EUTRA_FDD_TDD_Mode_Type v_EUTRA_FDD_TDD_Mode;
    var octetstring v_EncodedRlcPdu1;
    var octetstring v_EncodedRlcPdu2;
    var octetstring v_EncodedRlcPdu3;
    var octetstring v_EncodedRlcPdu4;
    var octetstring v_EncodedPdcpPdu;
    var SubFrameTiming_Type v_Timing;

    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    v_EUTRA_FDD_TDD_Mode := f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
    f_EUTRA_CellConfig_Def (eutra_Cell1); //@sic R5s100130
    //Configure cell with 2 AM DRBs
    f_EUTRA_Preamble (eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // creates cell and performs registration
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    f_EUTRA_LoopBackActivation_State4_7148();
    
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    // Configure SS in test mode
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    //@siclog "Step 1" siclog@
    // UL Grant of 32 bits
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync (eutra_Cell1, cs_TimingInfo_Now);
    // For LCH 1
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_12B)));
    v_EncodedRlcPdu1 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu2 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(0, 10), v_EncodedPdcpPdu));
    // For LCH 2
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_12B1)));
    v_EncodedRlcPdu3 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu4 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(0, 10), v_EncodedPdcpPdu));

    //@siclog "Step 2" siclog@
    //@sic R5s100066
    v_Timing := f_EUTRA_GetNextSendOccasion (eutra_Cell1);
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, 0),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB2, v_EncodedRlcPdu1))));

    
    //@siclog "Steps 3 - 5 - 5A" siclog@
    // preconfig SS for UL grant of 32 bits;
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        f_EUTRA_PeriodicCyclicULGrantTransmission (eutra_Cell1,
                                                   cs_TimingInfo((v_Timing.SFN.Number+6) mod 1024, 3),
                                                   0, 2, 50, 3); // Nprb = 2, Itbs = 0     Table 7.1.7.2.1-1 of 36.213
        //Imcs = 0 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213 */
        // period of 50 ms; 10 ms periodic BSR timer and 5 RTT =40 ms tolerance as per 36.508 clause 6.7
        
        
      } else
      {
        f_EUTRA_PeriodicCyclicULGrantTransmission (eutra_Cell1,
                                                   cs_TimingInfo((v_Timing.SFN.Number+6) mod 1024, 1), // Subframe 1 suitable for grant trasmission, further 6 also suitable;
                                                   0, 2, 65, 3); /* Nprb = 1, Itbs = 9          Table 7.1.7.2.1-1 of 36.213
                                                                  * Imcs = 9 -> Itbs = 9   MCS index of table 8.6.1-1 of 36.213 */
        // period of 65= ms; 10 ms periodic BSR timer and 5 RTT tolerance [5*11 for TDD configuration 1)as per 36.508 clause 6.7
        // this results in grant transmissions in subframes 6 and 1 hence data in 7 and 2 subframes
      }
    //@siclog "Step 4" siclog@
    DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo((v_Timing.SFN.Number+6) mod 1024, 7),
                                        {cr_MAC_PDU_2Padding_ShortBSR('01'B,'000011'B)}));
    //@siclog "Step 6" siclog@
    if (v_EUTRA_FDD_TDD_Mode == TDD)
      {
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+13) mod 1024, 2),
                                            {cr_MAC_PDU_2Padding_ShortBSR('01'B,'000011'B)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 6: UE is sending short BSR");
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+19) mod 1024, 7),
                                            {cr_MAC_PDU_2Padding_ShortBSR('01'B,'000011'B)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 6: UE is sending short BSR");
      } else //FDD
      {
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+11) mod 1024, 7),
                                            {cr_MAC_PDU_2Padding_ShortBSR('01'B,'000011'B)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 6: UE is sending short BSR");
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+16) mod 1024, 7),
                                            {cr_MAC_PDU_2Padding_ShortBSR('01'B,'000011'B)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 6: UE is sending short BSR");
        
      };
    //@siclog "Step 7 void" siclog@
    //@siclog "Step 8" siclog@
    v_Timing := f_EUTRA_GetNextSendOccasion (eutra_Cell1);
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, 0),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu3))));
    
    //@siclog "Steps 8A - 9" siclog@
    // preconfig SS for UL grant of 32 bits;
    if (v_EUTRA_FDD_TDD_Mode == FDD)
    {
      f_EUTRA_PeriodicCyclicULGrantTransmission (eutra_Cell1,
                                                 cs_TimingInfo((v_Timing.SFN.Number+6) mod 1024, 3),
                                                 0, 2, 50, 3); // Nprb = 2, Itbs = 0     Table 7.1.7.2.1-1 of 36.213
      // Imcs = 0 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213 */
      // period of 50 ms; 10 ms periodic BSR timer and 5 TTI tolerance as per 36.508 clause 6.7
      
                                                              
    } else
      {
        f_EUTRA_PeriodicCyclicULGrantTransmission (eutra_Cell1,
                                                   cs_TimingInfo((v_Timing.SFN.Number+6) mod 1024, 1), // Subframe 1 suitable for grant trasmission, further 6 also suitable;
                                                   0, 2, 65, 3); /* Nprb = 1, Itbs = 9          Table 7.1.7.2.1-1 of 36.213
                                                                  * Imcs = 9 -> Itbs = 9   MCS index of table 8.6.1-1 of 36.213 */
        // period of 65= ms; 10 ms periodic BSR timer and 5 TTI tolerance [5*11 for TDD configuration 1)as per 36.508 clause 6.7
        // this results in grant transmissions in subframes 6 and 1 hence data in 7 and 2 subframes
      }
    //@siclog "Step 8B" siclog@
    DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo((v_Timing.SFN.Number+6) mod 1024, 7),
                                        {cr_MAC_PDU_LongBSR(?,'000011'B,'000011'B,?)}));
    //@siclog "Step 10" siclog@
    if (v_EUTRA_FDD_TDD_Mode == TDD)
      {
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+13) mod 1024, 2),
                                            {cr_MAC_PDU_LongBSR(?,'000011'B,'000011'B,?)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 10: UE is sending short BSR");
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+19) mod 1024, 7),
                                            {cr_MAC_PDU_LongBSR(?,'000011'B,'000011'B,?)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 10: UE is sending short BSR");
      } else //FDD
      {
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+11) mod 1024, 7),
                                            {cr_MAC_PDU_LongBSR(?,'000011'B,'000011'B,?)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 10: UE is sending short BSR");
        DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                            cr_TimingInfo((v_Timing.SFN.Number+16) mod 1024, 7),
                                            {cr_MAC_PDU_LongBSR(?,'000011'B,'000011'B,?)}));
        f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 10: UE is sending short BSR");
        
      };
    //@siclog "Step 10A" siclog@
    f_EUTRA_OneULGrantTransmission( eutra_Cell1,
                                    cs_TimingInfo_Now,
                                    7, 3);  //results in a grant of 328 bits= 41 B
    // RLC PDU = 12B PDCP SDU + 2 PDCP H + 2 RLC H= 16 B
    // Minimum MAC header = 3 Byte; total 2*16+3=35B=280 bits; left 48 bits
    
    //
    //@siclog "Step 11" siclog@
    alt {
      // 2B SBR+ 4 B MAC SH + 1 B MAC Pad SH+ 16 B+ 16 B+ 2 B Pad = 41 B with short BSR
      [] DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                            tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_ShortBSR_2Subheader_Short_Padding (?,?,
                                                                                            tsc_LchId_DRB2,int2bit(16, 7), v_EncodedRlcPdu2, // UE shall poll
                                                                                            tsc_LchId_DRB1,int2bit(16, 7), v_EncodedRlcPdu4,// UE shall poll
                                                                                            cr_Octet2_Any)}))
        {
        }
      [] DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_ShortBSR_2Subheader_Short_Padding (?,?,
                                                                                            tsc_LchId_DRB1,int2bit(16, 7), v_EncodedRlcPdu4,// UE shall poll
                                                                                            tsc_LchId_DRB2,int2bit(16, 7), v_EncodedRlcPdu2, // UE shall poll
                                                                                              cr_Octet2_Any)}))
        {
        }
      // 4B LBR+ 3 B MAC SH + 2 B MAC Pad SH+ 16 B+ 16 B =41 B with Long BSR
      [] DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_LongBSR_2PaddingSubheader_2RLCPDU (?,
                                                                                            ?, ?,?,
                                                                                            tsc_LchId_DRB2, v_EncodedRlcPdu2, // UE shall poll
                                                                                            tsc_LchId_DRB1,v_EncodedRlcPdu4)}))       // UE shall poll
        {
        }
      [] DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                             tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_LongBSR_2PaddingSubheader_2RLCPDU (?,
                                                                                            ?, ?,?,
                                                                                            tsc_LchId_DRB1, v_EncodedRlcPdu4, // UE shall poll
                                                                                            tsc_LchId_DRB2,v_EncodedRlcPdu2)}))       // UE shall poll
        {
        }
    };
    f_RLC_Status_PDU_Tx(tsc_LchId_DRB1,1);
    f_RLC_Status_PDU_Tx(tsc_LchId_DRB2,1);
    
    f_EUTRA_TestBody_Set(false);
    //test body ends
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB in DL only
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NormalMode); //@sic R5s100272
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@
    
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
  }; // end of 7.1.4.8
  
  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.10
   * @status    APPROVED
   */
  function f_TC_7_1_4_10_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
       7.1.4.10 : MAC-Padding */
    var octetstring v_EncodedRlcPdu, v_EncodedRlcPdu1;
    var octetstring v_EncodedPdcpPdu;
    
    var C_RNTI v_C_RNTI;
    var SubFrameTiming_Type v_Timing;
    
    timer t_Watchdog := 5.0;
    //var integer v_DlBandwidth := 25;//for 5 MHz
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    //v_NRBDL := f_ConvertDL_BandwidthToInteger(f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1));
    f_EUTRA_Preamble (eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    // periodicBSR-Timer set as infinity is ToDo.
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // creates cell and performs registration
    
    f_EUTRA_LoopBackActivation_State4_Def_DisableBSR_PHR(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    // Preconfigures SS for RACH response for RAR and contention resolution
    //@sic R5-101079
    f_EUTRA_SS_ConfigRachProcedure (eutra_Cell1, omit, cs_RachProcedureConfig_CRNTI(f_EUTRA_CellInfo_GetRAR_TA(eutra_Cell1),
                                                                                    f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1), // @sic R5-103846 sic@
                                                                                    0, 4, 1, 1)); // Riv =0 => RB start =0, Nprb =1; IMCS =4 => 56 bits RAR grant
    //Contention resolution grant Imcs =1 and Nprb =1 => grant =24 bits
    
    
    // to configure UL Grant in RAR as 56 bits
    // config for PReamble reception indication
    f_EUTRA_SS_ConfigRachPreambleIndMode (eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    
    //@siclog "Step 1" siclog@
    // SS ignores scheduling requests and does not allocate any uplink grant
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync (eutra_Cell1, cs_TimingInfo_Now);
    v_C_RNTI := f_EUTRA_CellInfo_GetC_RNTI(eutra_Cell1);
    
    //@siclog "Step 4" siclog@
    // Pre config SS for UL Grant of 176 bits  //R5-094195
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            3, 3);    /* Nprb = 3, Itbs = 3          Table 7.1.7.2.1-1 of 36.213
                                                                       * Imcs = 3 -> Itbs = 3   MCS index of table 8.6.1-1 of 36.213 */
    //@siclog "Step 2" siclog@
    //R5-094195
    // MAC PDU (AMD PDU)
    // MAC Header = 2B Padding + 1B MAC SH= 3B
    // MAC SDU  = 10B => RLC SDU= 8, PDCP SDU= 6
    // Total MAC PDU = 2 + 1 + 10 B = 13B = 104b
    
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_6B)));
    v_EncodedRlcPdu  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu1  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(0, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_1SubHeader_2Padding_RLCPDU( tsc_LchId_DRB1,
                                                                                                   v_EncodedRlcPdu))));
    
    //@siclog "Step 5" siclog@
    // Check contents of 2
    //R5-094195
    //176 bits = 22 bytes = 10 MAC SDU + 2 MAC SH + 2 ShortBSR (1 SH +1 Control Element) LongBSR + 8 Padding (1 SH + 7 payload)
    t_Watchdog.start;
    DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_ShortBSR_1Subheader(?,
                                                                        ?,
                                                                        cdr_MAC_PDU_SubHeader_Short_SDU_LCID_Length_MoreSubHeaders(tsc_LchId_DRB1,
                                                                                                                                   int2bit(10, 7)),
                                                                        (v_EncodedRlcPdu, v_EncodedRlcPdu1),
                                                                        cr_Octet7_Any)}
                                        ));
    
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 5");
    t_Watchdog.stop;
    
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 1);
    //step8: pre config SS for UL Grant of 120 bits
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            0, 5);   /* Nprb = 5, Itbs = 0          Table 7.1.7.2.1-1 of 36.213
                                                                      * Imcs = 0 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213 */
    
    //@siclog "Step 6" siclog@
    //R5-094195
    //MAC PDU (AMD PDU)
    // MAC Header = 1 + 1Padding = 2 bytes.
    // MAC SDU's  = 13 => RLC SDU= 11, PDCP SDU= 9
    // Total MAC PDU = 13 + 2 B = 15B = 120b
    
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_9B)));
    v_EncodedRlcPdu  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_1SubHeader_1Padding( tsc_LchId_DRB1,
                                                                                            v_EncodedRlcPdu))));
    //@siclog "Step 9" siclog@
    // Check contents of 6
    //120 bits = 15 bytes = 13 + 1 SH + 1 Padding
    t_Watchdog.start;
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any, {cr_MAC_PDU_1SubHeader_1Padding(tsc_LchId_DRB1, cr_Octet13_Any)}));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 9");
    t_Watchdog.stop;
    
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 2);
    
    //@siclog "Step 10" siclog@
    //R5-094195
    //MAC PDU (AMD PDU)
    // MAC Header = 1B
    // MAC SDU's  = 10 => RLC SDU= 8, PDCP SDU= 6
    // Total MAC PDU = 10 + 1 = 11B = 88b
    
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN2, crs_PDCP_SDU_6B)));
    v_EncodedRlcPdu  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(2, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1,
                                                                                             v_EncodedRlcPdu))));
    //@siclog "Steps 11 - 12" siclog@ UL Grant of 120 bits; 120 bits grant already configured in step 8
    
    /* f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
       cs_TimingInfo_Now,
       0, 5); // Nprb = 5, Itbs = 0          Table 7.1.7.2.1-1 of 36.213
       // Imcs = 0 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213
       */
    
    //@siclog "Step 13" siclog@
    // check contents of 10  //R5-094195
    //120 bits = 15 bytes = (2B Padd + 1ShortBSR SH + 1MAC SH + 1 ShortBSR Element + 10 MAC SDU ) -> note 3
    t_Watchdog.start;
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_ShortBSR_2Padding_RLCPDU(tsc_LchId_DRB1,
                                                                             ?, ?,
                                                                             cr_Octet10_Any)}));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 13");
    t_Watchdog.stop;
    
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1,3);
    
    f_EUTRA_StopULGrantTransmission (eutra_Cell1, cs_TimingInfo_Now);     // to stop SS transmitting PUCCH Synch
    
    //@siclog "Step 14" siclog@
    v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1);   // at least 100ms in advance
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_TimingAdvance_0)));
    
    //@siclog "Step 15" siclog@
    //MAC PDU (AMD PDU)
    // MAC Header = 1  bytes.
    // MAC SDU's  = 14 => RLC SDU= 12, PDCP SDU= 10
    // Total MAC PDU = 1 + 14 B = 15B = 120b
    v_Timing := f_EUTRA_TimingInfoAdd (v_Timing, 710);      // 750 is Time alignment timer -40 ms
    //[between 40 to 50 ms less than time alignment timer]=710 ms
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN3, crs_PDCP_SDU_10B)));
    v_EncodedRlcPdu  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(3, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu1 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(3, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu))));
    
    //@siclog "Step 16" siclog@
    t_Watchdog.start;
    SYSIND.receive(car_PRACH_Preamble_IND_Any (eutra_Cell1,?));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 16");
    t_Watchdog.stop;
    
    
    //@siclog "Step 17" siclog@
    //RAR taken care due of to SS preconfiguration
    
    //@siclog "Step 18" siclog@
    // check step 15
    t_Watchdog.start;
        t_Watchdog.start;
    alt
      {
        []DRB.receive ( car_DRB_COMMON_IND_MAC (eutra_Cell1, tsc_RbId_DRB1, cr_TimingInfo_Any,
                                                {cr_MAC_PDU_2Padding_ShortBSR_CRNTI_CNTRLElem(v_C_RNTI)}))
          {
            t_Watchdog.stop;
            f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 18");
          };
        []DRB.receive ( car_DRB_COMMON_IND_MAC (eutra_Cell1, tsc_RbId_DRB1, cr_TimingInfo_Any,
                                                {cr_MAC_PDU_2Padding_CRNTI_CNTRLElem_ShortBSR(v_C_RNTI)}))
          {
            t_Watchdog.stop;
            f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 18");
          };
      }
    
    //@siclog "Step 19" siclog@
    // To receive the short BSR resulting because of 16 bit grant for step 4 of RACH procedure
    t_Watchdog.start;
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_ShortBSR_1Padding('10'B, ?)}));
    //TBD grant transmision assumption now changed to 24.
    //@sic R5-101079
    t_Watchdog.stop;
    
    //@siclog "Step 20" siclog@
    //automatically taken care of
    // Note UE is not configured to send SR's hence an immediate UL Grant is allocated
    // A Risk TBD if UE re performs a PRACH procedure
    f_EUTRA_OneULGrantTransmission( eutra_Cell1,
                                    cs_TimingInfo_Now,
                                    4, 2);    /* Nprb = 2, Itbs = 4     Table 7.1.7.2.1-1 of 36.213
                                               * Imcs = 4 -> Itbs = 0   MCS index of table 8.6.1-1 of 36.213 */
    
    
    //@siclog "Step 21" siclog@
    t_Watchdog.start;
    DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1, tsc_RbId_DRB1, cr_TimingInfo_Any,
                                        {cr_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, (v_EncodedRlcPdu,v_EncodedRlcPdu1))}));//@sic R5s100043
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 21");
    t_Watchdog.stop;
    
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1,4);
    
    f_EUTRA_TestBody_Set(false);
    //test body ends
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // config for stop of PReamble reception indication
    f_EUTRA_SS_ConfigRachPreambleIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NormalMode); //@sic R5s100272
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    // start normal UL grant transmission
    // Preconfigure SS for RACH response for default RAR and contention resolution
    // Due to PRACH procedure in step 17 and 18, UE is UL timing synchronised but SR resources are not existing.
    // Bring UE in SRS configured state to be capable of sending Scheduling Requests
    f_RRC_ConnectionReconfiguration_SRS_Config(eutra_Cell1);
    
    
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@
    
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
    
  };// end of 7.1.4.10


  function f_TC_7_1_4_11_EUTRA() runs on EUTRA_PTC
  {
        /* L2/MAC
        7.1.4.11 : Correct HARQ process handling
        */

    var integer j;
    var octetstring v_EncodedPDCPPDU, v_EncodedRLCPDU;
    var MAC_PDU_Type v_MAC_PDU;
    var SubFrameTiming_Type v_Timing, v_Timing2;
    //var RedundancyVersion_Type v_RedundancyVersion :=0;
    var DRB_COMMON_IND v_DRB_COMMON_IND;
    var EUTRA_FDD_TDD_Mode_Type  v_EUTRA_FDD_TDD_Mode ;
    var integer v_RTT := 8; // Round trip time 8 for FDD and 10 for TDD
    var UL_TransRetransmissionList_Type v_UL_TransRetransmissionList1 := { { NewTransmission := true },
                                                                           { ReTransmissionNonAdaptive := true }, // RV 2
                                                                           { ReTransmissionNonAdaptive := true}, // RV 3
                                                                           { ReTransmissionNonAdaptive := true }, // RV 1
                                                                           { ReTransmissionNonAdaptive := true }, // RV 0
                                                                           { ReTransmissionNonAdaptive := true },  // RV 2
                                                                           { ReTransmissionAdaptive := 1 },      // RV 1
                                                                           { ReTransmissionAdaptive := 3 }       // RV 3
    };

    /* var UL_TransRetransmissionList_Type v_UL_TransRetransmissionList2 := { { ReTransmissionAdaptive := 1 },
                                                                           { ReTransmissionAdaptive := 3 } }; */

    var UL_TransRetransmissionList_Type v_UL_TransRetransmissionList3 := { { ReTransmissionAdaptive := 0 } }; //sic@ R5s100522 sic@
    var template (omit) DRB_ToAddModList v_DRB_ToAddModList:= omit;
    timer t_Watchdog         := 5.0;              // Local wait Timer

    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    v_EUTRA_FDD_TDD_Mode := f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
    //initialise RTT for TDD
    if (v_EUTRA_FDD_TDD_Mode == TDD)
      {
        v_RTT := 10;
      }

    f_EUTRA_CellConfig_Def (eutra_Cell1);
    f_EUTRA_Preamble(eutra_Cell1,STATE2A_TESTLOOP_ModeA);
    // creates cell and performs registration
    
    // Disable AS ciphering on UE side.
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
        v_DRB_ToAddModList[0] := cs_508_DRB_ToAddMod_Common(tsc_DRB1,
                                                        cs_508_PDCP_Config_DRB_AM,
                                                        cs_508_RLC_Config_DRB_AM(cds_TX_AM_RLC_t_PollRetransmit(ms250)),
                                                        cs_508_LogicalChannelConfig_DRB_AM);

    f_EUTRA_GenericRbEst_Common(eutra_Cell1,0,0,v_DRB_ToAddModList,cs_508_MAC_MainConfig_RBC_maxHARQ_Tx8_Explicit_DrxL,omit,omit,omit); //R5-095104
    
    f_EUTRA_CloseUE_TestLoopModeA(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    // Configures SS DRB1 in MAC test mode.
    //f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);
    // Configure SS to report Scheduling Requests

    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
        f_EUTRA_StopULGrantTransmission_PUCCH_Sync ( eutra_Cell1,cs_TimingInfo_Now );//@sic R5s100522 sic@

    // preconfig SS for PHICH mode
    f_SS_ConfigPhich_TestMode (eutra_Cell1,
                               cs_Phich_ExplicitMode(cs_HARQ_ModeList_4Nack_Ack_2Nack));
    
    v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1,200);//@sic R5s100522 sic@
    //@siclog "Step 1" siclog@
    // 1 MAC PDU = 1 RLC PDU;  1 RLC PDU =1 PDCP PDU
    // MAC Header = 1B
    // 1 MAC SDU of 14 => RLC SDU= 12, PDCP SDU = 10
    // Total MAC PDU = 1 + 14  = 15B = 120b (best fit)
    v_EncodedPDCPPDU := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_10B)));
    v_EncodedRLCPDU  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPDCPPDU));
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRLCPDU))));
    
    //@siclog "Step 2 void" siclog@
    /*t_Watchdog.start;
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "");
    t_Watchdog.stop;*/
    //@siclog "Step 3" siclog@
    // Pre config SS for UL Grant of 120 bits
    //Note the function is not used here to guarantee sub frame 9
    //schedule 59 sub frames in future;
    //Subframe 9 means for both FDD and TDD, UE send ul data in sub frame 3.
    v_Timing.SFN.Number := (v_Timing.SFN.Number +5) mod 1024;
    v_Timing.Subframe.Number :=9;


    f_EUTRA_OneULGrantTransmission_DCI( eutra_Cell1,
                                        cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), //@sic R5s100522 sic@
                                        cs_DciInfo_CcchDcchDtchUL_Explicit_RV(4, 2, /* Nprb = 2, Itbs = 4          Table 7.1.7.2.1-1 of 36.213
                                                                                       Imcs = 4 -> Itbs = 4   MCS index of table 8.6.1-1 of 36.213 */
                                                                              v_UL_TransRetransmissionList1) );
    //Preconfig for step 24
    //@siclog "Step 24" siclog@
    //sic@ R5s100522 sic@
     v_Timing2.SFN.Number := (v_Timing.SFN.Number + 80)mod 1024;
     v_Timing2.Subframe.Number :=v_Timing.Subframe.Number;
      f_EUTRA_OneULGrantTransmission_RV(eutra_Cell1,
                                      cs_TimingInfo(v_Timing2.SFN.Number, v_Timing2.Subframe.Number),
                                      4, 2,//Nprb = 2, Itbs = 4
                                      v_UL_TransRetransmissionList3);
    //@siclog "Steps 17 - 20" siclog@
    // Preconfig SS
    /*v_Timing2:=f_EUTRA_TimingInfoAdd(v_Timing, (6 * v_RTT)); // suitable for step 17
    f_EUTRA_OneULGrantTransmission_RV(eutra_Cell1,
                                      cs_TimingInfo(v_Timing2.SFN.Number, v_Timing2.Subframe.Number),
                                      4, 2,//Nprb = 2, Itbs = 4
                                      v_UL_TransRetransmissionList2);
    //v_Timing3:=f_EUTRA_TimingInfoAdd(v_Timing, (7 * v_RTT))// suitable for step 20
    //uplink frame timing */
    v_Timing := f_GetSubFrameNumForULData(v_EUTRA_FDD_TDD_Mode, v_Timing);
    //@siclog "Step 4" siclog@
    t_Watchdog.start;
    alt {
       []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1, cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                      {cr_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, cr_Octet14_Any)})) -> value v_DRB_COMMON_IND
         {
           f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 4");
           //v_Timing := v_DRB_COMMON_IND.Common.TimingInfo.SubFrame;
           //v_EncodedMACPDU:= v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.MacPdu[0].SduList[0];
           v_MAC_PDU:= v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.MacPdu[0];
           v_Timing := f_EvaluateNext_UL_TransmissionForHARQ_Process(v_Timing ,v_EUTRA_FDD_TDD_Mode); // Next TTI.
          
        }
    };
    for (j:=0; j<4; j:= j+1)
      {
        //@siclog "Steps 6 - 8 - 10 - 12" siclog@
        //@siclog "Step 14 void" siclog@
        alt {
          []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                    cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                    {v_MAC_PDU})) -> value v_DRB_COMMON_IND
            {
              f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Steps 6 - 8 - 10 - 12");
              v_Timing := f_EvaluateNext_UL_TransmissionForHARQ_Process(v_Timing, v_EUTRA_FDD_TDD_Mode); // Next TTI.
             
            }
        };
        //@siclog "Steps 7 - 9 - 11" siclog@
        //@siclog "Step 13 void" siclog@
        //@siclog "Step 15" siclog@
        // Automatically taken care off
        
      }// End of For loop
    // Note v_Timing holds timing for step 16;
    //Timing for step 18
    v_Timing := f_EvaluateNext_UL_TransmissionForHARQ_Process(v_Timing, v_EUTRA_FDD_TDD_Mode);
    
    //@siclog "Steps 16 - 18" siclog@
    alt {
      [] DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                                 tsc_RbId_DRB1,
                                                 cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                  {v_MAC_PDU}))
        {
          f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "step 18");
          v_Timing := f_EvaluateNext_UL_TransmissionForHARQ_Process(v_Timing, v_EUTRA_FDD_TDD_Mode); // Next
          
        }
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1, cr_TimingInfo_Any,
                                                {v_MAC_PDU})) -> value v_DRB_COMMON_IND
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 16: UE is Retrasmitting MAC PDU");
          // it is assumed SS will route MAC PDU corresponding to step 16[if any] before step 18
          // if step 18 is executed, then it is confirmed step 16 is passed
        }
    };
        
    //@siclog "Step 19" siclog@
    // Automatically taken care off

    //@siclog "Step 21" siclog@
    DRB.receive (car_DRB_COMMON_IND_MAC(eutra_Cell1,tsc_RbId_DRB1,
                                            cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                             {v_MAC_PDU}));
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 21");

    
    //@siclog "Step 22" siclog@
    // Automatically taken care off
    //@siclog "Step 23, 25" siclog@
    //sic@ R5s100522 sic@
    v_Timing := f_EvaluateNext_UL_TransmissionForHARQ_Process(v_Timing ,v_EUTRA_FDD_TDD_Mode);
    v_Timing2 := f_GetSubFrameNumForULData(v_EUTRA_FDD_TDD_Mode,v_Timing2);
    alt {
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                 {v_MAC_PDU}))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 23: UE is Retransmitting MAC PDU");
          t_Watchdog.stop;
        }
      
      [] DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                 cr_TimingInfo(v_Timing2.SFN.Number, v_Timing2.Subframe.Number),
                                                  {v_MAC_PDU}))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 25: UE is Retransmitting MAC PDU");
          t_Watchdog.stop;
        }
      
      [] DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                 cr_TimingInfo(v_Timing2.SFN.Number, v_Timing2.Subframe.Number),
                                                  {cr_MAC_PDU_NoSDU}))
        {
               t_Watchdog.stop;
        }
      
    };
    //@siclog "Step 25a" siclog@
    //@sic R5-104162 sic@
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 1);
    f_SS_ConfigPhich_TestMode (eutra_Cell1, cs_PhichTestModeNormal);

    //@siclog "Step 26" siclog@
    //sic@ R5s100522 sic@
    v_Timing:= f_GetSubFrameNumForULGrant(v_EUTRA_FDD_TDD_Mode, v_Timing2);
    v_Timing.SFN.Number := (v_Timing.SFN.Number + 395) mod 1024;// 3.95 +0.05 =4 seconds to keep intact the process and accomodate 2 seconds delay timer
    v_Timing :=f_GetSubFrameNumForULGrant_DiffHarqProcess(v_EUTRA_FDD_TDD_Mode, v_Timing);
    v_EncodedPDCPPDU := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_10B)));
    v_EncodedRLCPDU  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPDCPPDU));
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo(v_Timing.SFN.Number, 0),// DL subframe
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRLCPDU))));
    
    //schedule 50 to 59 sub frames in future;

    v_Timing.SFN.Number := (v_Timing.SFN.Number +5) mod 1024;
    

    
    
    //@siclog "Step 26" siclog@
    

    //@siclog "Step 27 void" siclog@

    //@siclog "Step 28" siclog@
    f_EUTRA_OneULGrantTransmission( eutra_Cell1,
                                    cs_TimingInfo( v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                    // 30 ms should be sufficient for UE to send scheduling Req
                                    4, 2); /* Nprb = 2, Itbs = 4          Table 7.1.7.2.1-1 of 36.213
                                              Imcs = 4 -> Itbs = 4   MCS index of table 8.6.1-1 of 36.213 */
    
    //@siclog "Step 30" siclog@
    v_Timing2:=f_EUTRA_TimingInfoAdd(v_Timing,  v_RTT); // suitable for step 30
    f_EUTRA_OneULGrantTransmission_RV(eutra_Cell1,cs_TimingInfo(v_Timing2.SFN.Number, v_Timing2.Subframe.Number),
                                      4, 2,//Nprb = 2, Itbs = 4
                                      cs_TransRetransmissionListUL_Def);
    t_Watchdog.start;
    /*
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?))
        {
          f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "");
          repeat;
        } */

    //@siclog "Step 29" siclog@
    v_Timing := f_GetSubFrameNumForULData(v_EUTRA_FDD_TDD_Mode, v_Timing);
    alt {
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                {cr_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, cr_Octet14_Any)})) -> value v_DRB_COMMON_IND
        {
          f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 29");
          v_MAC_PDU:= v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.MacPdu[0];
          t_Watchdog.stop;
        }
    };
    //@siclog "Step 31" siclog@
    v_Timing := f_GetSubFrameNumForULData(v_EUTRA_FDD_TDD_Mode, v_Timing2);
    
    t_Watchdog.start;
    alt {
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1, tsc_RbId_DRB1,
                                                cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                {v_MAC_PDU}))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 31: UE is Retransmitting MAC PDU");
          t_Watchdog.stop;
        }
      []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                {cr_MAC_PDU_NoSDU}))
        {
            // UE transmits a mostly padding MAC PDU
          t_Watchdog.stop;
        }
    };
    //@siclog "Step 32" siclog@
    //@sic R5-104162 sic@
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 2);
    
    f_EUTRA_TestBody_Set(false);
    //test body ends
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    
    //f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    // Configure SS to report Scheduling Requests
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB in DL only
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1,cs_MAC_TestMode_NormalMode); //@sic R5s100272
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);

    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@

    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
    
  } // end of 7.1.4.11
  
  
  function f_TC_7_1_4_12_EUTRA() runs on EUTRA_PTC
  /* L2/MAC
     7.1.4.12 : MAC reset-UL
  */
  {
    var SYSTEM_IND v_ReceivedSYSIND;
    var float v_SchedulingRequestWindowSize;
    var SubFrameTiming_Type v_Timing, v_Timing2;
    
    timer t_Watchdog:=5.0; // General purpose wait timer

    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
     // Config Cell 1 for 1 AM DRB
     // Set up cell 1 power as per T0
    f_EUTRA_SetCellPower(eutra_Cell1,-90,cs_TimingInfo_Now);
    // Configure cell with one AM and UM DRB
    f_EUTRA_CellConfig_DefPlusUM (eutra_Cell1);
    // Configure cell with one AM and UM DRB
    f_EUTRA_CellInfo_InitMaxReferencePower(eutra_Cell2, -80);
    f_EUTRA_CellConfig_DefPlusUM  (eutra_Cell2);
    // Bring UE to idle updated state
    f_EUTRA_Preamble(eutra_Cell1, STATE2A_TESTLOOP_ModeA);

    f_EUTRA_RbEst_508_UM(eutra_Cell1);  // Initialization, call setup, DRB loopback

    // TBD: specific contents for     maxHARQ-Tx to 28.
    // TBD: Specific contents for  discardTimer to be 50 ms.
    // TBD: step to establish UM DRB is not good
    // TBD: dsr-TransMax to be configured as Max value 64
    //issues to be raised in Mantis
    // TBD issue with clean establishment of UM bearer.
    f_EUTRA_CloseUE_TestLoopModeA(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    // to configure SS to report reception of HARQ ACK or NACK
    f_SS_ConfigSchedulingRequestIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Enable);
    // configure SS to send no response on RACH preamble reception
    f_EUTRA_SS_ConfigRachProcedure (eutra_Cell1,
                                    omit,
                                    cs_RachProcedureConfig_NoResponse(f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1) ));// @sic R5-103846 sic@
    
    // to enable reception of SR in cell 2
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell2, tsc_L1Mac_IndicationMode_Enable);
    // preconfig for RACH procedure
    f_EUTRA_SS_ConfigRachProcedure (eutra_Cell2,tsc_C_RNTI_Def2, cs_RachProcedureConfig_Def(omit,f_EUTRA_CellInfo_GetRAR_TA(eutra_Cell2),f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1) ));// @sic R5-103846 sic@
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    //@siclog "Step 1" siclog@
    // To stop UL Grant Transmision
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1,cs_TimingInfo_Now);
    // 38 bytes PDCP SDU +2 byte PDCP header
    // 2 bytes RLC Header +2 byte MAC Header =352 bits, nearest TB  size =372 => padding =24 bits
    // 1 byte padding header and 2 bits padding
    // step 5 sequence is changed to facilitate SS implementations.
    f_EUTRA_SetCellPower (eutra_Cell2, -80, cs_TimingInfo_Now);
    //@siclog "Step 2" siclog@
    DRB.send (cas_DRB_COMMON_REQ_PDCP_SDU (eutra_Cell1,tsc_RbId_DRB2, cs_TimingInfo_Now,  cs_PDCP_SDUList_1 (crs_PDCP_SDU_L39)));
    
    //@siclog "Step 3" siclog@
    t_Watchdog.start;// 100 ms
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?));
    f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 3");
    t_Watchdog.stop;

    //@siclog "Step 4" siclog@
    v_Timing := f_EUTRA_GetCurrentTiming(eutra_Cell1);
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?)) -> value v_ReceivedSYSIND
        {
          //Check if the received SR is within a window of 100 ms
          v_Timing2 := v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          v_SchedulingRequestWindowSize := f_EUTRA_SetTimerToleranceMin(eutra_Cell1, 0.05); //50 ms to wait for SR
          if (f_EUTRA_SubFrameTimingDuration_Float(v_Timing, v_Timing2) < v_SchedulingRequestWindowSize) {
            repeat;
          }
        }
      []t_Watchdog.timeout
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 4");
        }
    };
    
    //@siclog "Step 5" siclog@
    // Preconfigured
    //@siclog "Step 6" siclog@
    //@sic R5s100240 sic@
    f_EUTRA_508RRC_ConnReconfigHO_IntraLTE (eutra_Cell1,
                                            eutra_Cell2);
    
    //@siclog "Step 7" siclog@
    // Check: does the UE transmit a RRCConnectionReconfigurationComplete message to confirm the reconfiguration of the radio resources?
    t_Watchdog.start;
    SRB.receive(car_SRB1_RrcPdu_IND(eutra_Cell2, cr_508_RRCConnectionReconfigurationComplete(tsc_RRC_TI_Def)));
    f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 7");
    t_Watchdog.stop;
    
    // default grant config
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell2, cs_TimingInfo_Now);
    
    //@siclog "Step 8" siclog@
     t_Watchdog.start(2.0);
     alt {
       []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell2, ?))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 8: UE is  sending SR ");
          t_Watchdog.stop;
        }
       [] t_Watchdog.timeout
         {
           f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 8");
         }
     };
     // prepare cell 1 for PRACH operation at handover
     f_EUTRA_SS_ConfigRachProcedure (eutra_Cell1,tsc_C_RNTI_Def, cs_RachProcedureConfig_Def(omit,f_EUTRA_CellInfo_GetRAR_TA(eutra_Cell1),f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1) ));// @sic R5-103846 sic@
     // preconfig cell 2 to send HARQ NACK's
     f_SS_ConfigPhich_TestMode(eutra_Cell2,cs_Phich_ExplicitMode (cs_HARQ_ModeList_28Nack));
     //@siclog "Step 9" siclog@
     DRB.send (cas_DRB_COMMON_REQ_PDCP_SDU (eutra_Cell2,tsc_RbId_DRB2, cs_TimingInfo_Now,  cs_PDCP_SDUList_1 (crs_PDCP_SDU_L39_1)));
     //@siclog "Step 10" siclog@
     t_Watchdog.start;
     SYSIND.receive(car_SchedulingReq_IND (eutra_Cell2, ?));
     f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 10");
     t_Watchdog.stop;
     
    //@siclog "Step 11" siclog@
    // Automatically taken care off
    //@siclog "Step 12" siclog@
     t_Watchdog.start;
     DRB.receive (car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell2,tsc_RbId_DRB2,cr_TimingInfo_Any,
                                                         cr_PDCP_SDUList_1(crs_PDCP_SDU_L39_1)));
     f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 12");
     t_Watchdog.stop;
     
     // Note even though UE may potentially do multiple retransmissions, the corresponding UL PDCP SDU's are not sent to
     // TTCN due to duplicate detection in SS RLC/PDCP.
     
     //@siclog "Step 13" siclog@
     // Automatically taken care off
     //@siclog "Step 14" siclog@
     //@sic R5s100240 sic@
     f_EUTRA_508RRC_ConnReconfigHO_IntraLTE (eutra_Cell2,
                                             eutra_Cell1);

     //@siclog "Step 15" siclog@
     // Check: does the UE transmit a RRCConnectionReconfigurationComplete message to confirm the reconfiguration of the radio resources?
     t_Watchdog.start;
     SRB.receive(car_SRB1_RrcPdu_IND(eutra_Cell1, cr_508_RRCConnectionReconfigurationComplete(tsc_RRC_TI_Def)));
     f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 15");
     t_Watchdog.stop;
     
     //stop grant in cell 2 and sart def grant in cell 1
     f_EUTRA_StopULGrantTransmission(eutra_Cell2,cs_TimingInfo_Now);
     f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
     //@siclog "Step 16" siclog@
     t_Watchdog.start(2.0);
     alt {
       [] DRB.receive (car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell1,tsc_RbId_DRB2,cr_TimingInfo_Any,?))
         {
           f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 16: UE is  sending loop back data ");
           t_Watchdog.stop;
         }
       [] t_Watchdog.timeout
         {
           f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 16");
         }
     };
    //@siclog "Step 17" siclog@
    DRB.send (cas_DRB_COMMON_REQ_PDCP_SDU (eutra_Cell1,tsc_RbId_DRB2, cs_TimingInfo_Now,
                                           cs_PDCP_SDUList_1 (crs_PDCP_SDU_L39)));
    //@siclog "Step 18" siclog@
    t_Watchdog.start;
    SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?));
    f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 18");
    t_Watchdog.stop;
    
    //@siclog "Step 19" siclog@
    // Automatically taken care off
    //@siclog "Step 20" siclog@
    t_Watchdog.start;
    DRB.receive (car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell1,
                                                  tsc_RbId_DRB2,
                                                  cr_TimingInfo_Any,
                                                  cr_PDCP_SDUList_1(crs_PDCP_SDU_L39)));
    f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 20");
    t_Watchdog.stop;
    
    //test body ends
    f_EUTRA_TestBody_Set(false);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // preconfig cell 2 for PHICH normal mode
    f_SS_ConfigPhich_TestMode(eutra_Cell2,cs_PhichTestModeNormal);
    // to disable reception of SR in cell 2
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell2, tsc_L1Mac_IndicationMode_Disable);
    // to disable reception of SR in cell 1
    f_SS_ConfigSchedulingRequestIndMode(eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@
    
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
    //Remove the cell2, non camping
    //@sic R5-103847 taken care in postamble now sic@
    
  } // end of 7.1.4.12
  
  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.13
   * @status    APPROVED
   */
  function f_TC_7_1_4_13_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
       7.1.4.13 : MAC PDU header handling
    */
    var octetstring v_EncodedRlcPdu,v_EncodedRlcPdu2,v_EncodedRlcPdu3,v_EncodedRlcPdu4;
    var octetstring v_EncodedPdcpPdu, v_EncodedPdcpPdu2;
    timer t_Watchdog := 5.0;              // Local wait Timer
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    f_EUTRA_Preamble(eutra_Cell1, STATE2A_TESTLOOP_ModeA);
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // creates cell and performs registration
    
    f_EUTRA_LoopBackActivation_State4_7147_71413();
    
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.

    //@siclog "Step 1" siclog@
    // SS ignores scheduling requests and does not allocate any uplink grant
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1, cs_TimingInfo_Now);
    
    //@siclog "Step 4" siclog@
    // Pre config SS for UL Grant of 1096 bits = 137B
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            8, 8); // Nprb = 8, Itbs = 8          Table 7.1.7.2.1-1 of 36.213
    // Imcs = 8 -> Itbs = 8   MCS index of table 8.6.1-1 of 36.213
    
    //@siclog "Step 2" siclog@
    //MAC PDU (MAC Subheader (LCID=00011; F=0; L=127), AMD PDU)
    // MAC Header = 1B + 1B Pad
    // MAC SDU's  = 127 => RLC SDU= 125, PDCP SDU= 123
    // Total MAC PDU = 2 + 127 B = 1032b
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue(cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_L123)));
    v_EncodedRlcPdu  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu2 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(0, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_1SubHeader_1Padding(tsc_LchId_DRB1, v_EncodedRlcPdu))));
    //@siclog "Step 3" siclog@
    // Taken care automatically
    
    //1096 bits = 137B = 2B MAC SubHeader + 127B MAC SDU +  2B ShortBSR + 6B padding
    //@siclog "Step 5" siclog@
    // Check step2
    t_Watchdog.start;
    DRB.receive (car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_ShortBSR_1Subheader(('10'B,'01'B),//R5s-100068; As UE after transmission has no data left on any DRB, it can include any configured LCG
                                                                        ?,
                                                                        cdr_MAC_PDU_SubHeader_Short_SDU_LCID_Length_MoreSubHeaders(tsc_LchId_DRB1,
                                                                                                                                   int2bit(127, 7)),
                                                                        (v_EncodedRlcPdu, v_EncodedRlcPdu2),
                                                                        cr_Octet5_Any)}));
    //@sic R5s090362 sic@
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 5");
    t_Watchdog.stop;
    
    //R5-095077
    //@siclog "Step 5A" siclog@
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 1);
    
    //@siclog "Step 8" siclog@
    // Preconfig SS for UL Grant of 1096 bits = 137B
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            8, 8); // Nprb = 8, Itbs = 8          Table 7.1.7.2.1-1 of 36.213
    // Imcs = 8 -> Itbs = 8   MCS index of table 8.6.1-1 of 36.213
    
    //@siclog "Step 6" siclog@
    // MAC PDU (MAC Subheader (LCID=00011, AMD PDU)
    // MAC Header = 1 = 1 bytes.
    // MAC SDU's  = 128 => RLC SDU= 126, PDCP SDU= 124
    // Total MAC PDU =  1 + 128 = 129B = 1032b
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue(cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_124B)));
    v_EncodedRlcPdu  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu2 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(1, 10), v_EncodedPdcpPdu));
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu))));
    
    //@siclog "Step 7" siclog@
    // Taken care automatically
    
    //@siclog "Step 9" siclog@
    // Check step6
    //1096 bits = 137B = 3MAC Header + 128B MAC SDU +  2B ShortBSR+ 4 B Padding
    t_Watchdog.start;
    DRB.receive( car_DRB_COMMON_IND_MAC(eutra_Cell1,
                                        tsc_RbId_DRB1,
                                        cr_TimingInfo_Any,
                                        {cr_MAC_PDU_ShortBSR_1Subheader(('10'B,'01'B), //R5s-100068; As UE after transmission has no data left on any DRB, it can include any configured LCG
                                                                        ?,
                                                                        cdr_MAC_PDU_SubHeader_Long_SDU_LCID_Length_MoreHeaders(tsc_LchId_DRB1,
                                                                                                                               int2bit(128, 15)),
                                                                        (v_EncodedRlcPdu, v_EncodedRlcPdu2),
                                                                        cr_Octet3_Any)}));
    //@sic R5s090362 sic@
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 9");
    t_Watchdog.stop;
    
    //@siclog "Step 10" siclog@
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 2);

    //@siclog "Step 13" siclog@
    // Pre config SS fo UL Grant of 176 bits
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            1, 5);  // Nprb = 5, Itbs = 1          Table 7.1.7.2.1-1 of 36.213
    // Imcs = 1 -> Itbs = 1   MCS index of table 8.6.1-1 of 36.213
    //@siclog "Step 11" siclog@
    // Tx with 2 subheaders, first with LCID '00011' and another with LCID '00100'
    // 1 MAC PDU = 2 RLC PDU; 1RLC PDU =1 PDCP PDU
    // 1 MAC SDU of 11 => RLC SDU= 9, PDCP SDU = 7
    // 1 MAC SDU of 8 => RLC SDU= 6, PDCP SDU = 4
    // Total MAC PDU = (2+1) + 11 + 8  = 22B =  176 b
    
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue(cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN2, crs_PDCP_SDU_7B)));
    v_EncodedRlcPdu  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(2, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu3 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(2, 10), v_EncodedPdcpPdu));
    
    v_EncodedPdcpPdu2 := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN0, crs_PDCP_SDU_4B)));
    v_EncodedRlcPdu2  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(0,10), v_EncodedPdcpPdu2));//@sic R5s090362 sic@
    v_EncodedRlcPdu4  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(0,10), v_EncodedPdcpPdu2));//@sic R5s090362 sic@
    
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_2RLCPDU_ShortSubHeaders(tsc_LchId_DRB1,
                                                                                               tsc_LchId_DRB2,
                                                                                               v_EncodedRlcPdu,
                                                                                               v_EncodedRlcPdu2))));
    
    //@siclog "Step 12" siclog@
    // Taken care automatically
    //@siclog "Step 14" siclog@
    // Check of step 11
    //@sic R5-101070 MAC SDU's for DRB1 and 2 can be in any order
    
    t_Watchdog.start;
    alt {
      [] DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_2RLCPDU_ShortSubHeaders(tsc_LchId_DRB1,
                                                                                 tsc_LchId_DRB2,
                                                                                 int2bit(11, 7),
                                                                                 (v_EncodedRlcPdu,v_EncodedRlcPdu3),
                                                                                 (v_EncodedRlcPdu2,v_EncodedRlcPdu4))}
                                             )) //@sic R5s090362 sic@
        { }// DRB1 + DRB2
      //@sic R5s100116
      [] DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_2RLCPDU_ShortSubHeaders(tsc_LchId_DRB2,
                                                                                 tsc_LchId_DRB1,
                                                                                 int2bit(8, 7),
                                                                                 (v_EncodedRlcPdu2,v_EncodedRlcPdu4),
                                                                                 (v_EncodedRlcPdu,v_EncodedRlcPdu3))}
                                             )) //@sic R5s090362 sic@
        {}   // DRB2 + DRB1
    } // end of alt
    
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 14");
    t_Watchdog.stop;
    
    //@siclog "Steps 15 - 16" siclog@
    // Status PDU to be tranmsitted for DRB 1 as 3 and DRB 2 as 1
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 3);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2, 1);
    
    //@siclog "Step 19" siclog@
    // Pre config SS for UL Grant of 256 bits
    f_EUTRA_StartExplicitULGrantTransmissionOnSR_Reception( eutra_Cell1,
                                                            cs_TimingInfo_Now,
                                                            6, 3);  // Nprb = 3, Itbs = 6          Table 7.1.7.2.1-1 of 36.213
    // Imcs = 6 -> Itbs = 6   MCS index of table 8.6.1-1 of 36.213
    //@siclog "Step 17" siclog@
    // Transmit with 2 subheaders, first with LCID '00011' and another more with LCID '00100'
    // 1 MAC PDU = 2 RLC PDU; 1RLC PDU =1 PDCP PDU
    // MAC Header = 2+ 1 = 3 bytes.
    // 1 MAC SDU of 10 => RLC SDU = 8, PDCP SDU = 6
    // 1 MAC SDU of 9 => RLC SDU = 7, PDCP SDU = 5
    // Total MAC PDU = (2+1) + 10 + 9  = 22B = 176
    v_EncodedPdcpPdu  := f_PDCP_PDU_Encvalue(cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN3, crs_PDCP_SDU_6B)));
    v_EncodedRlcPdu   := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(3, 10), v_EncodedPdcpPdu));
    v_EncodedRlcPdu3  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(3, 10), v_EncodedPdcpPdu));
    //@sic  R5s100049
    v_EncodedPdcpPdu2 := f_PDCP_PDU_Encvalue(cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_5B)));
    v_EncodedRlcPdu2  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu2));
    v_EncodedRlcPdu4  := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_Poll, int2bit(1, 10), v_EncodedPdcpPdu2));

    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_2RLCPDU_ShortSubHeaders( tsc_LchId_DRB1,
                                                                                                tsc_LchId_DRB2,
                                                                                                v_EncodedRlcPdu,
                                                                                                v_EncodedRlcPdu2))));
    
    //@siclog "Step 18" siclog@
    // Taken care automatically
    
    //@siclog "Step 20" siclog@
    // Check of step 16
    //@sic R5-101070 MAC SDU's for DRB1 and 2 can be in any order
    //4B LongBSR + (2+2)ShortSubheaders + (10B+9B) MAC SDUs + 5Padding[1 SH+ 4 PAd] = 32B = 256b
    //2B ShortBSR + (2+2)ShortSubheaders + (10B+9B) MAC SDUs + 7Padding[1 SH+ 6 PAd] = 32B = 256b
    t_Watchdog.start;
    alt {
      [] DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_LongBSR_2Subheader_Short_Padding(?, ?, ?, ?,
                                                                                          tsc_LchId_DRB1,int2bit(10, 7), (v_EncodedRlcPdu,v_EncodedRlcPdu3),
                                                                                          tsc_LchId_DRB2,int2bit(9, 7), (v_EncodedRlcPdu2,v_EncodedRlcPdu4),
                                                                                          cr_Octet4_Any)}
                                             ))
        {
          // Long BSR + DRB1+ DRB2+Pad
        }
      [] DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_LongBSR_2Subheader_Short_Padding(?, ?, ?, ?,
                                                                                          tsc_LchId_DRB2,int2bit(9, 7), (v_EncodedRlcPdu2,v_EncodedRlcPdu4),
                                                                                          tsc_LchId_DRB1,int2bit(10, 7), (v_EncodedRlcPdu,v_EncodedRlcPdu3),
                                                                                          cr_Octet4_Any)}
                                             ))
        {
          // Long BSR + DRB2+ DRB1+Pad
        }
      [] DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_ShortBSR_2Subheader_Short_Padding(('01'B,'10'B), ?,
                                                                                           tsc_LchId_DRB1,int2bit(10, 7), (v_EncodedRlcPdu,v_EncodedRlcPdu3),
                                                                                           tsc_LchId_DRB2,int2bit(9, 7), (v_EncodedRlcPdu2,v_EncodedRlcPdu4),
                                                                                           cr_Octet6_Any)}
                                             ))
        {
          // Short BSR + DRB1+ DRB2+Pad
        }
      [] DRB.receive(car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                             cr_TimingInfo_Any,
                                             {cr_MAC_PDU_ShortBSR_2Subheader_Short_Padding(('01'B,'10'B), ?,
                                                                                           tsc_LchId_DRB2,int2bit(9, 7), (v_EncodedRlcPdu2,v_EncodedRlcPdu4),
                                                                                           tsc_LchId_DRB1,int2bit(10, 7), (v_EncodedRlcPdu,v_EncodedRlcPdu3),
                                                                                           cr_Octet6_Any)}
                                             ))
        {
          // Short BSR + DRB2+ DRB1+Pad
        }
    }// end of alt statement
    //@sic R5s090362 sic@
    f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 20");
    t_Watchdog.stop;
    
    //@siclog "Steps 21 - 22" siclog@
    // Status PDU to be tranmsitted for DRB1 as 4 and DRB2 as 2
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB1, 4);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2, 2);
    
    f_EUTRA_TestBody_Set(false);
    //test body ends
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // step to configure SS RLC/PDCP and MAC in No header manipulation mode on SS Side for DRB
    // to enable proper SS routing in UL..
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1, cs_MAC_TestMode_NormalMode); //@sic R5s100272
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@
    
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
    
  }; // End of 7.1.4.13
  
  function f_TC_7_1_4_14_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
       7.1.4.14 : Correct HARQ process handling: TTI Bundling
    */
    var octetstring v_EncodedPdcpPdu, v_EncodedRlcPdu ;
    var SubFrameTiming_Type v_Timing, v_Timing1,v_TimingUL[12] ;
    var EUTRA_FDD_TDD_Mode_Type  v_EUTRA_FDD_TDD_Mode;
    var integer j :=0;

    var SR_PUCCH_ResourceIndex_Type v_Sr_PUCCH_ResourceIndex;
    var SR_ConfigIndex_Type v_SR_ConfigIndex ; //@sic R5-102177 sic@

    timer t_Watchdog := 5.0;
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    v_EUTRA_FDD_TDD_Mode := f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
    v_Sr_PUCCH_ResourceIndex := f_EUTRA_CellInfo_GetSR_PUCCH_ResourceIndex(eutra_Cell1);
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    f_EUTRA_Preamble(eutra_Cell1,STATE2A_TESTLOOP_ModeA);
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // creates cell and performs registration
    f_EUTRA_LoopBackActivation_State4_Def_DisableBSR_PHR(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    v_SR_ConfigIndex := f_EUTRA_CellInfo_GetSR_ConfigIndex (eutra_Cell1 ); //@sic R5-102177 sic@
    // Go to state 4 to return no data in UL
    // Specific message contents configuration at UE
    f_RRC_ConnectionReconfiguration_MAC_Physical_Reconfig(eutra_Cell1,tsc_RRC_TI_Def,
                                                          cs_TimingInfo_Now,cs_MAC_MainConfig_Explicit_7_1_4_14,
                                                          cs_PhysicalConfigDedicated_DSR_Transmax(v_Sr_PUCCH_ResourceIndex,v_SR_ConfigIndex));
    //prose does not specify DSR trans max as 64
    // Configure SS DL in MAC Test Mode
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1,cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    
    //enabling TTI bundling at UE
    f_SS_TTI_Bundle_Configure (eutra_Cell1,cs_TimingInfo_Now,true,f_EUTRA_CellInfo_GetDL_ChBandwidth(eutra_Cell1),f_EUTRA_CellInfo_GetCombination(eutra_Cell1) );
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true,layer2); // @sic R5-101050.
    // step 1, to stop UL Grant Transmision
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1,cs_TimingInfo_Now);
    // store cell info parameters for C-RNTI
    // preconfig SS for PHICH mode
    f_SS_ConfigPhich_TestMode (eutra_Cell1,
                               cs_Phich_ExplicitMode(cs_HARQ_ModeList_Nack_2Ack));
    // First NACK at the 4th Tx and then Ack at the 4Th Tx.
    v_Timing := f_EUTRA_GetCurrentTiming(eutra_Cell1);
    // calculate future timing info
    v_Timing.SFN.Number := (v_Timing.SFN.Number + 11) mod 1024; // app 110 ms in future
    v_Timing.Subframe.Number := 0; // selected as DL frame in all TDD configurations
    //@siclog "Step 1" siclog@
    // 36B PDCP SDU + 2B PDCP H + 2B RLC H + 1B MAc SH = 41B =328 bits
    v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_36B)));
    v_EncodedRlcPdu := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu));
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB1,
                                          cs_TimingInfo_Now,
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu))));
    //@siclog "Step 3" siclog@
    v_Timing.SFN.Number:= (v_Timing.SFN.Number+4) mod 1024;
    v_Timing.Subframe.Number := 4;
    f_EUTRA_OneULGrantTransmission(eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), 7, 3);
    // sub frame 4 means for both FDD and TDD default comb 1, the k=4 i.e. UL transmission in SF 8
    
    v_TimingUL[0].SFN.Number := v_Timing.SFN.Number;
    v_TimingUL[0].Subframe.Number := 8; //For both FDD and TDD UL/DL Config1 (SFFDD,SFTDD) (8,8)
    v_TimingUL[1]:= f_EvaluateNext_UL_TTI(v_TimingUL[0],v_EUTRA_FDD_TDD_Mode);  //(9,2)
    v_TimingUL[2]:= f_EvaluateNext_UL_TTI(v_TimingUL[1],v_EUTRA_FDD_TDD_Mode);  //(0,3)
    v_TimingUL[3]:= f_EvaluateNext_UL_TTI(v_TimingUL[2],v_EUTRA_FDD_TDD_Mode);  //(1,7)
    // HARQ NACK Transmission  delta KK=(4,4) =>( 5,1)
    //Next Grant option Transmission  Delta l(5,3)=> (0,4)
    //Next UL Transmisiion delta k(4,4) =>(4,8)
    // Total Delat FDD= 4+5+4 =13 SF [Last ReTx -> First Tx)
    //TDD= 4+3+4= 11 SF
    if(v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_TimingUL[4].SFN.Number := (v_TimingUL[3].SFN.Number + (v_TimingUL[3].Subframe.Number+ 13) mod 10) mod 1024;
        v_TimingUL[4].Subframe.Number := (v_TimingUL[3].Subframe.Number+ 13) mod 10;
      }
    else
      {
        v_TimingUL[4].SFN.Number := (v_TimingUL[3].SFN.Number + (v_TimingUL[3].Subframe.Number+ 11) mod 10) mod 1024;
        v_TimingUL[4].Subframe.Number := (v_TimingUL[3].Subframe.Number+ 11) mod 10;
      }
    //(4,8)
    v_TimingUL[5]:= f_EvaluateNext_UL_TTI(v_TimingUL[4],v_EUTRA_FDD_TDD_Mode);//(5,2)
    v_TimingUL[6]:= f_EvaluateNext_UL_TTI(v_TimingUL[5],v_EUTRA_FDD_TDD_Mode);//(6,3)
    v_TimingUL[7]:= f_EvaluateNext_UL_TTI(v_TimingUL[6],v_EUTRA_FDD_TDD_Mode);//(7,7)
    // HARQ Ack Transmission  delta KK=(4,4) =>( 1,1)
    // Next UL Grnat transmission delta (5,3) =>(6,4)
    //Next UL Transmission delta (4,4) => (0,8)
    //Total Delata FDD =4+5+4 =13
    //Total Delta TDD = 4+3+4 =11
    if(v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_TimingUL[8].SFN.Number := (v_TimingUL[7].SFN.Number + (v_TimingUL[7].Subframe.Number+ 13) mod 10) mod 1024;
        v_TimingUL[8].Subframe.Number := (v_TimingUL[7].Subframe.Number+ 13) mod 10;
      }
    else
      {
        v_TimingUL[8].SFN.Number := (v_TimingUL[7].SFN.Number + (v_TimingUL[7].Subframe.Number+ 11) mod 10) mod 1024;
        v_TimingUL[8].Subframe.Number := (v_TimingUL[7].Subframe.Number+ 11) mod 10;
      }
    //(0,8)
    v_TimingUL[9]:= f_EvaluateNext_UL_TTI(v_TimingUL[8],v_EUTRA_FDD_TDD_Mode);//(1,2)
    v_TimingUL[10]:= f_EvaluateNext_UL_TTI(v_TimingUL[9],v_EUTRA_FDD_TDD_Mode);//(2,3)
    v_TimingUL[11]:= f_EvaluateNext_UL_TTI(v_TimingUL[10],v_EUTRA_FDD_TDD_Mode);//(3,7)
    
    // Occasion for Grant in step 9
    // Total delta for grant from v_TimingUL[7] FDD= 4+5 =9; TDD = 4+3 =7;
    if(v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing1.SFN.Number := (v_TimingUL[7].SFN.Number + (v_TimingUL[7].Subframe.Number+ 9) mod 10) mod 1024;
        v_Timing1.Subframe.Number := (v_TimingUL[7].Subframe.Number+ 9) mod 10;
      }
    else
      {
        v_Timing1.SFN.Number := (v_TimingUL[7].SFN.Number + (v_TimingUL[7].Subframe.Number+ 7) mod 10) mod 1024;
        v_Timing1.Subframe.Number := (v_TimingUL[7].Subframe.Number+ 7) mod 10;
      } //(6,4)
    //@siclog "Step 9" siclog@
    f_EUTRA_OneULGrantTransmission(eutra_Cell1,cs_TimingInfo(v_Timing1.SFN.Number, v_Timing1.Subframe.Number), 30, 3);
    
    //@siclog "Steps 2 - 4 - 5 - 7 - 10 - 11 - 13" siclog@
    t_Watchdog.start;
    alt {
      []SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?))
        {
          repeat;
        }
      [j< 12]DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                     cr_TimingInfo(v_TimingUL[j].SFN.Number, v_TimingUL[j].Subframe.Number),
                                                     {cr_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu)}))
        {
          f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Steps 2 - 4 - 5 - 7 - 10 - 11: UL MAC PDU received");
          j:= j+1;
          repeat;
        }
      [j>=12] DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,tsc_RbId_DRB1,
                                                   cr_TimingInfo_Any,
                                                   {cr_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB1, v_EncodedRlcPdu)}))
        {
          f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step: 13: UE is sending UL MAC PDU");
        }
      [] t_Watchdog.timeout
        {
          if (j==12)
            {
              f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Steps 2 - 4 - 5 - 7 - 10 - 11: All UL MAC PDU's received");
            }
          else
            {
              f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Steps 2 - 4 - 5 - 7 - 10 - 11 - 13: Test Failed");
            }
        }
    };
    //@siclog "Steps 6 - 8 - 12" siclog@
    // Automatically taken care by SS
    
    //test body ends
    f_EUTRA_TestBody_Set(false);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // Configure SS DL in MAC Test Mode
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB1,cs_MAC_TestMode_NormalMode); //@sic R5s100272
    
    // configure SS for default grant allocation
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@
    
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
  };
  
  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.15
   * @status    APPROVED
   */
  function f_TC_7_1_4_15_EUTRA() runs on EUTRA_PTC
  { /* 7.1.4.15 : UE Power Headroom Reporting [Periodic reporting] */
    var boolean v_Flag1 := true;
    var boolean v_Flag2 := true;
    var SubFrameTiming_Type v_Timing1, v_Timing2;
    var SYSTEM_IND v_ReceivedSYSIND;
    timer t_Watchdog := 5.0;
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    // Config Cell 1 for 1 AM DRB
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    // Bring UE to idle updated state
    f_EUTRA_Preamble(eutra_Cell1, STATE2_IDLEUPDATE);
    // Bring UE to state 3
    f_EUTRA_RbEst_Def(eutra_Cell1);
    // to configure SS to start report reception of  Power head room report
    f_SS_ConfigPowerHeadRoomIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Enable);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true);
    //@siclog "Step 1" siclog@
    f_EUTRA_PeriodicULGrantTransmission( eutra_Cell1,
                                         cs_TimingInfo_Now ,// immediate effect
                                         12, // Imcs => Mod =16QAM Arbitrarily selected forTBS =776
                                         4, // Nprb
                                         1);  // period =1 => every allowed TTI
    //@siclog "Step 2" siclog@
    SRB.send(cas_SRB1_RrcPdu_REQ(eutra_Cell1,
                                 cs_TimingInfo_Now,
                                 cs_RRCConnectionReconfiguration_RadioResConfig (tsc_RRC_TI_Def,
                                                                                 cs_RadioResourceConfigDedicated_MAC({ explicitValue  := cs_MAC_MainConfiguration_PHR_Enable71415}, omit, omit))));
    
    
    //@siclog "Steps 3 - 4" siclog@
    t_Watchdog.start;
    
    alt {
      [v_Flag1] SRB.receive(car_SRB1_RrcPdu_IND(eutra_Cell1, cr_508_RRCConnectionReconfigurationComplete(tsc_RRC_TI_Def)))
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 4");
          v_Flag1 := false;
          if (v_Flag2) // PHR not received yet
            {
              repeat;
            }
          else
            {
              t_Watchdog.stop;
            }
        }
      [v_Flag2] SYSIND.receive(car_PHR_IND(eutra_Cell1,cr_TimingInfo_Any, ?))->value v_ReceivedSYSIND
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 3");
          v_Timing1:= v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          v_Flag2 := false;
          if (v_Flag1) // Connection Reconfiguration not received yet
            {
              repeat;
            }
          else
            {
              t_Watchdog.stop;
            }
        }
    }
    
    //@siclog "Step 5" siclog@
    t_Watchdog.start;
    alt {
      [] SYSIND.receive(car_PHR_IND(eutra_Cell1,cr_TimingInfo_Any, ?))->value v_ReceivedSYSIND
        //store the timing information check the PHR before and now occur in 200 ms + tolerance.
        {
          v_Timing2:= v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          t_Watchdog.stop;
          if (f_EUTRA_SubFrameTimingCheckDuration (eutra_Cell1, f_EUTRA_SubFrameTimingDuration(v_Timing1, v_Timing2), 200))
            // to be corrected the tolerance
            {
              f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 5: received PHR ");
            }
          else
            {
              f_EUTRA_SetVerdictFailOrInconc (__FILE__, __LINE__, "Step 5: UE sent Power head room report but wrong periodicPHR-Timer");
            }
        }
    }
    
    //@siclog "Step 6" siclog@
    SRB.send(cas_SRB1_RrcPdu_REQ(eutra_Cell1,
                                 cs_TimingInfo_Now,
                                 cs_RRCConnectionReconfiguration_RadioResConfig (tsc_RRC_TI_Def,
                                                                                 cs_RadioResourceConfigDedicated_MAC ({ explicitValue := cs_MAC_MainConfiguration_PHR_Disable}, omit, omit))));
    //@siclog "Step 7" siclog@
    t_Watchdog.start;
    SRB.receive(car_SRB1_RrcPdu_IND(eutra_Cell1, cr_508_RRCConnectionReconfigurationComplete(tsc_RRC_TI_Def)));
    f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 7");
    t_Watchdog.stop;
    
    //@siclog "Step 8" siclog@
    t_Watchdog.start(2.0);
    alt {
      []SYSIND.receive(car_PHR_IND(eutra_Cell1, cr_TimingInfo_Any, ?))
        {
          f_EUTRA_SetVerdictFailOrInconc (__FILE__, __LINE__, "Step 8: UE is continuing to send Power head room report ");
          t_Watchdog.stop;
        }
      [] t_Watchdog.timeout
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 8");
        }
    };
    
    //test body ends
    f_EUTRA_TestBody_Set(false);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // to configure SS to stop report reception of  Power head room report
    f_SS_ConfigPowerHeadRoomIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Disable);
    // configure SS for default grant allocation
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);//@sic R5s100456 sic@
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E2_CONNECTED );//@sic R5-103875 sic@
  } // end of
  
  /*
   * @desc      REFERENCE TS 36.523-1 clause 7.1.4.16
   * @status    APPROVED
   */
  function f_TC_7_1_4_16_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
     * 7.1.4.16 : UE Power Headroom Reporting [DL_Pathloss change reporting]
     */
    var boolean v_Flag1 := true, v_Flag2 := true;
    var SubFrameTiming_Type v_Timing, v_Timing1, v_Timing2, v_Timing3;
    var SYSTEM_IND v_ReceivedSYSIND;
    var ReferenceCellPower_Type v_CurrentCellPower ;
    var AbsoluteCellPower_Type v_CurrentRefPowerLevel ;
    var Frequency_IE_Type v_Frequency_IE; // R5-104535
    var ChannelBandwidthDependency_Type v_ChBandDependency; // R5-104535
    
    timer t_Watchdog := 5.0;
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    // Config Cell 1 for 1 AM DRB
    f_EUTRA_CellConfig_Def (eutra_Cell1);
    // Bring UE to idle updated state
    f_EUTRA_Preamble (eutra_Cell1, STATE2_IDLEUPDATE);
    // Bring UE to state 3
    f_EUTRA_RbEst_Def(eutra_Cell1);
    // to configure SS to start report reception of  Power head room report
    f_SS_ConfigPowerHeadRoomIndMode (eutra_Cell1, tsc_L1Mac_IndicationMode_Enable);
    v_CurrentCellPower := f_EUTRA_CellInfo_GetCellPower(eutra_Cell1);
    v_CurrentRefPowerLevel := v_CurrentCellPower.MaxReferencePower;
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true);
    //@siclog "Step 1" siclog@
    f_EUTRA_PeriodicULGrantTransmission(eutra_Cell1,
                                        cs_TimingInfo_Now ,// immediate effect
                                        12, // Imcs => Mod =16QAM Arbitrarily selected forTBS =776
                                        4, // Nprb
                                        1);  // period =1 => every allowed TTI
    //@siclog "Step 2" siclog@
    // R5-104535
    /* SRB.send(cas_SRB1_RrcPdu_REQ(eutra_Cell1,
                                 cs_TimingInfo_Now,
                                 cs_RRCConnectionReconfiguration_RadioResConfig (tsc_RRC_TI_Def,
                                                                                 cs_RadioResourceConfigDedicated_MAC ({ explicitValue := cs_MAC_MainConfiguration_PHR_Enable71416},
                                                                                                                      omit,
                                                                                                                      omit)))); */
    v_Frequency_IE := f_EUTRA_CellInfo_GetFrequencyIEs ( eutra_Cell1 );
    v_ChBandDependency:= f_EUTRA_BandDependentParam ( v_Frequency_IE.DL_ChBandwidth,
                                                      v_Frequency_IE.UL_ChBandwidth );
    SRB.send(cas_SRB1_RrcPdu_REQ(eutra_Cell1,
                                 cs_TimingInfo_Now,
                                 cs_RRCConnectionReconfiguration_Common (tsc_RRC_TI_Def,
                                                                         cs_Measurement_Config(v_Frequency_IE.UL_DL_Earfcn.dl_CarrierFreq,
                                                                                               v_ChBandDependency.AllowedMeasBandwidth),
                                                                         omit,
                                                                         cs_RadioResourceConfigDedicated_MAC ({ explicitValue := cs_MAC_MainConfiguration_PHR_Enable71416},
                                                                                                              omit,
                                                                                                              omit),
                                                                         omit)));

    //@siclog "Steps 3 - 4" siclog@
    t_Watchdog.start;
    //R5-094432
    alt {
      [v_Flag1] SRB.receive(car_SRB1_RrcPdu_IND(eutra_Cell1, cr_508_RRCConnectionReconfigurationComplete(tsc_RRC_TI_Def)))
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 3");
          v_Flag1 := false;
          if (v_Flag2) // PHR not received yet
            {
              repeat;
            }
          else
            {
              t_Watchdog.stop;
            }
        }
      [v_Flag2] SYSIND.receive(car_PHR_IND(eutra_Cell1,cr_TimingInfo_Any, ?)) -> value v_ReceivedSYSIND
        {
          f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 3");
          v_Timing1:= v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          v_Flag2 := false;
          if (v_Flag1) // Connection Reconfiguration not received yet
            {
              repeat;
            }
          else
            {
              t_Watchdog.stop;
            }
        }
    }
    //@siclog "Step 5" siclog@
    // Calculate future timing info
    v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1); //  100 ms in future
    f_EUTRA_SetCellPower(eutra_Cell1,
                         v_CurrentCellPower.MaxReferencePower - 5,
                         cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number));
    
   
    //@siclog "Steps 6 - 7" siclog@
    t_Watchdog.start;
    alt {
      [] SYSIND.receive(car_PHR_IND(eutra_Cell1, cr_TimingInfo_Any, ?)) -> value v_ReceivedSYSIND
        //store the timing information check the PHR before and now occur in 1000 ms +/- tolerance.
        {
          v_Timing2:= v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          t_Watchdog.stop;
          if (f_EUTRA_SubFrameTimingCheckDuration (eutra_Cell1, f_EUTRA_SubFrameTimingDuration(v_Timing1, v_Timing2), 1000))
            // to be corrected the tolerance
            {
              f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 7: received PHR ");
            }
          else
            {
              f_EUTRA_SetVerdictFailOrInconc (__FILE__, __LINE__, "Step 6: UE sent Power head room report but wrong periodicPHR-Timer");
            }
        }
    }
    //@siclog "Step 8" siclog@
    // Calculate future timing info
    v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1); //  100 ms in future
    f_EUTRA_SetCellPower(eutra_Cell1,
                         v_CurrentCellPower.MaxReferencePower,
                         cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number));
    //@siclog "Steps 9 - 10" siclog@
    t_Watchdog.start;
    alt {
      [] SYSIND.receive(car_PHR_IND(eutra_Cell1, cr_TimingInfo_Any, ?)) -> value v_ReceivedSYSIND
        //store the timing information check the PHR before and now occur in 1000 ms + tolerance.
        {
          v_Timing3:= v_ReceivedSYSIND.Common.TimingInfo.SubFrame;
          t_Watchdog.stop;
          if (f_EUTRA_SubFrameTimingCheckDuration(eutra_Cell1, f_EUTRA_SubFrameTimingDuration(v_Timing2, v_Timing3), 1000))
            // to be corrected the tolerance
            {
              f_EUTRA_PreliminaryPass(__FILE__, __LINE__, "Step 10: received PHR ");
            }
          else
            {
              f_EUTRA_SetVerdictFailOrInconc (__FILE__, __LINE__, "Step 9: UE sent Power head room report but wrong periodicPHR-Timer");
            }
        }
    };
    f_EUTRA_TestBody_Set(false);
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    // disable PHR reporting
    // to configure SS to stop report reception of  Power head room report
    f_SS_ConfigPowerHeadRoomIndMode (eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    // configure SS for default grant allocation
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    SRB.send(cas_SRB1_RrcPdu_REQ(eutra_Cell1,
                                 cs_TimingInfo_Now,
                                 cs_RRCConnectionReconfiguration_RadioResConfig(tsc_RRC_TI_Def,
                                                                                cs_RadioResourceConfigDedicated_MAC({ explicitValue := cs_MAC_MainConfiguration_PHR_Disable},
                                                                                                                    omit,
                                                                                                                    omit))));
    t_Watchdog.start;
    SRB.receive(car_SRB1_RrcPdu_IND(eutra_Cell1, cr_508_RRCConnectionReconfigurationComplete(tsc_RRC_TI_Def)));
    //f_EUTRA_PreliminaryPass(__FILE__, __LINE__, ""); R5-104796
    t_Watchdog.stop;
    
    
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E2_CONNECTED );//@sic R5-103875 sic@
  } // end of 7.1.4.16
  
  group Local_TC7142_Functions {
  
  
  function fl_ReceiveOneMACPDU_Length (CellId_Type p_CellId,
                                       RadioBearerId_Type p_RbId,
                                       template (present) TimingInfo_Type p_TimingInfo,
                                       template (present) MAC_PDU_Type p_MAC_PDU,
                                       integer p_MAC_PDU_Length) runs on EUTRA_PTC
  {
    var DRB_COMMON_IND v_DRB_COMMON_IND;
    var integer v_Received_Size;
    
    timer t_Watchdog := 5.0;
    
    t_Watchdog.start;
    
    alt {
      []DRB.receive (car_DRB_COMMON_IND_MAC (p_CellId,p_RbId,p_TimingInfo,{p_MAC_PDU}))-> value v_DRB_COMMON_IND
        {
          t_Watchdog.stop;
          v_Received_Size := lengthof (f_MAC_PDU_Encvalue (v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.MacPdu[0]));
          if (v_Received_Size == p_MAC_PDU_Length)
            {
              f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "");
            }
          else
            {
              f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "UE is MAC PDU of different size");
            }
        }
    };
  };
  
  function fl_ReceiveOneMACPDU_Length_T1AndNoPDUT2 (CellId_Type p_CellId,
                                                    RadioBearerId_Type p_RbId,
                                                    template (present) TimingInfo_Type p_TimingInfo,
                                                    template (present) TimingInfo_Type p_TimingInfoNo,
                                                    template (present) MAC_PDU_Type p_MAC_PDU,
                                                    integer p_MAC_PDU_Length) runs on EUTRA_PTC
  // p_TimingInfoNo is ahead of p_TimingInfo
  {
    var DRB_COMMON_IND v_DRB_COMMON_IND;
    var integer v_Received_Size;
    
    timer t_Watchdog := 5.0;
    
    t_Watchdog.start;
     alt {
       []DRB.receive (car_DRB_COMMON_IND_MAC (p_CellId,p_RbId,p_TimingInfoNo,{cr_MAC_PDU_Any}))
         {
           t_Watchdog.stop;
           f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "UE is Sending MAC PDU ");
         }
       []DRB.receive (car_DRB_COMMON_IND_MAC (p_CellId,p_RbId,p_TimingInfo,{p_MAC_PDU}))-> value v_DRB_COMMON_IND
         {
           t_Watchdog.stop;
           v_Received_Size := lengthof (f_MAC_PDU_Encvalue (v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.MacPdu[0]));
           if (v_Received_Size == p_MAC_PDU_Length)
             {
               f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "");
             }
           else
             {
               f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "UE is Sending MAC PDU of different size");
             }
         }
     };
   };

  } // end of group Local_TC7142_Functions
  
  
  function f_TC_7_1_4_2_EUTRA() runs on EUTRA_PTC
  { /* L2/MAC
       7.1.4.2 : Correct handling of UL assignment / semi persistent case
    */
    const C_RNTI tsc_SPS_RNTI := tsc_C_RNTI_Def2;
    // const integer tsc_SPS_SchedInterval := 16 ; //160 Sf the SPS schedule interval
    // const integer tsc_SF_Before := 8; //80 ms
    
    var SubFrameTiming_Type v_Timing, v_TimingY, v_TimingP, v_TimingQ;
    var octetstring v_EncodedRlcPdu1,v_EncodedPdcpPdu ;
    var EUTRA_FDD_TDD_Mode_Type  v_EUTRA_FDD_TDD_Mode ;
    var default v_MyDefaultVar := null;
    var template (value) SpsConfigUL_Type v_SpsConfigUL;
    
    timer t_Watchdog := 0.4;// 400 ms should be sufficient to receive HARQ ACK/NACK

    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_Init (c1);
    v_EUTRA_FDD_TDD_Mode := f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
    // @sic R5-096034 sic@
    f_EUTRA_CellConfig_DefPlusUM (eutra_Cell1);
    f_EUTRA_Preamble(eutra_Cell1,STATE2A_TESTLOOP_ModeA);
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // creates cell and performs registration
    f_EUTRA_RbEst_508_UM(eutra_Cell1);// Initialization, call setup, DRB loopback
    f_EUTRA_CloseUE_TestLoopModeA(eutra_Cell1, cs_UE_TestLoopModeA_LB_Setup_NoScaling);
    
    // Go to state 4 to return data in UL same as DL
    
     if (v_EUTRA_FDD_TDD_Mode == FDD)
       {
         v_SpsConfigUL :=   cs_SpsConfigUL_FDD;
       }
     else
       {
         v_SpsConfigUL :=   cds_SpsConfigUL_TDD;
       };
     
     
     // Default SPS configuration as in specific message contents.
     f_RRC_ConnectionReconfiguration_SPS_Config(eutra_Cell1,tsc_RRC_TI_Def,cs_TimingInfo_Now,
                                                cs_SPS_Config_UL(tsc_SPS_RNTI,cs_SPS_ConfigUL_Setup(v_SpsConfigUL)));
     // Configure SS DL in MAC Test Mode
     f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB2,cs_MAC_TestMode_NoHeaderManipulationDL_UL);
       
     
     // to configure SS to report reception of SR
     f_SS_ConfigSchedulingRequestIndMode (eutra_Cell1,tsc_L1Mac_IndicationMode_Enable);
     ///////////////////////////////////////////////////////////////////////////////////
     //      Test Body
     //////////////////////////////////////////////////////////////////////////////////
     f_EUTRA_TestBody_Set(true);
     // configure SS for stoping C-RNTI grant allocation
     f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1,cs_TimingInfo_Now);
     // To receive Scheduling Requests in alt step
     v_MyDefaultVar := activate(a_EUTRA_MAC_ScheduligReq(eutra_Cell1));
     // 320B PDCP SDU + 2B PDCP H + 2B RLC H + 1B MAC SH = 325B =2600 bits
     // => PDCP PDU =322 B
 
     // Step 4 52B,step 6  52B,step 9  72B,step 12 72B,step 17 72B Total =372 B leaves space of 50B for BSR's and other signalling
     v_EncodedPdcpPdu := f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_320B)));
     v_EncodedRlcPdu1 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll, int2bit(1, 10), v_EncodedPdcpPdu));
     v_TimingY := f_EUTRA_GetCurrentTiming(eutra_Cell1);
     v_TimingY.SFN.Number := (v_TimingY.SFN.Number + 11) mod 1024; // app 110 ms in future
     v_TimingY.Subframe.Number := 0; // all TDD support
     //@siclog "Step 1" siclog@
     DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                           tsc_RbId_DRB2,
                                           cs_TimingInfo(v_TimingY.SFN.Number,v_TimingY.Subframe.Number),
                                           cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB2, v_EncodedRlcPdu1))));
     
     v_TimingY.SFN.Number := (v_TimingY.SFN.Number + 6) mod 1024; // app 60 ms in future, to be suitable for Loop Back delay
     v_TimingY.Subframe.Number := 0; // results in UL transmission in SF 8 in both FDD and TDD default UL/DL configuration of 1
    // 52B PDCP Segment + 2B RLC Header + 1 MAC SH  = 55 Bytes=440b=>Imcs13=Itbs =12, Nprb =2
     v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,4); // 4 sub frames
     //@siclog "Step 3" siclog@
     f_SS_ActivateSPS_Grant (eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                             cs_UL_SPSInfo (tsc_SPS_RNTI,cs_SpsAssignmentUL (cs_DciInfo_CcchDcchDtchUL_Explicit(13, 2), v_SpsConfigUL))); // NDI =0
     
     //@siclog "Step 2" siclog@
     SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?));
     
     //@siclog "Step 4" siclog@
     v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,4); // 4 sub frames
     fl_ReceiveOneMACPDU_Length(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), cr_MAC_PDU_Any,55);
     f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,0);
     //@siclog "Step 5" siclog@
     // Automatically taken care by SS
     //@siclog "Step 8" siclog@
     // preconfig SS
     v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,244); // 244 sub frames;
     
     // 72B PDCP Segment + 2B RLC Header + 1 MAC SH  = 75 Bytes=600b=>Imcs16 =Itbs =15, Nprb =2
     f_SS_ActivateSPS_Grant (eutra_Cell1, cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                             cs_UL_SPSInfo (tsc_SPS_RNTI,cs_SpsAssignmentUL (cs_DciInfo_CcchDcchDtchUL_Explicit(16, 2), v_SpsConfigUL))); // NDI =0
     //@siclog "Step 6" siclog@
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,168); // 168 sub frames;
      } else
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,167); // 168 sub frames;
      }
    
    fl_ReceiveOneMACPDU_Length(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), cr_MAC_PDU_Any,55);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,1);
    
    //@siclog "Step 7" siclog@
    // Automatically taken care by SS
    
    //@siclog "Step 9" siclog@
    v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,248) ;// 248 sub frames;
    fl_ReceiveOneMACPDU_Length(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), cr_MAC_PDU_Any,75);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,2);
    //@siclog "Step 10" siclog@
    // Automatically taken care of
    //@siclog "Step 14" siclog@
    // Preconfig SS
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,484); // 484 sub frames;
      } else
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,481); // 481 sub frames;
      }
    f_SS_ActivateSPS_Grant (eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                            cs_UL_SPSInfo (tsc_SPS_RNTI,cs_SpsAssignmentUL (cs_DciInfo_CcchDcchDtchUL_Explicit(16, 2), v_SpsConfigUL, true))); // NDI is set as 1
    
    //@siclog "Steps 11 - 12" siclog@
    v_TimingP := f_EUTRA_TimingInfoAdd(v_TimingY,328); // 328 sub frames;
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,408); // 408 sub frames;
      } else
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,407); // 407 sub frames;
      }
    fl_ReceiveOneMACPDU_Length_T1AndNoPDUT2(eutra_Cell1,
                                            tsc_RbId_DRB2,
                                            cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                            cr_TimingInfo(v_TimingP.SFN.Number, v_TimingP.Subframe.Number),
                                            cr_MAC_PDU_Any,
                                            75);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2, 3);
    
    //@siclog "Step 13" siclog@
    //automatically taken care of
    
    //@siclog "Step 15" siclog@
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,488); // 408 sub frames;
      } else
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,487); // 407 sub frames;
      }
    fl_ReceiveOneMACPDU_Length(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo( v_Timing.SFN.Number, v_Timing.Subframe.Number),
                               cr_MAC_PDU_Any,75);
    // As retransmission no RLC ACK Sent
    //@siclog "Step 16" siclog@
    // Automatically taken care
    
    //@siclog "Step 17" siclog@
    v_Timing := f_EUTRA_TimingInfoAdd(v_TimingY,568); // 568 sub frames;
    fl_ReceiveOneMACPDU_Length(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo(v_TimingP.SFN.Number, v_TimingP.Subframe.Number), cr_MAC_PDU_Any,75);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,4);
    //@siclog "Step 18" siclog@
    // Already taken care
    
    //@siclog "Step 19" siclog@
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,724); // 724 sub frames;
      } else
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,721) ;// 721 sub frames;
      }
    // 52B PDCP Segment + 2B RLC Header + 1 MAC SH  = 55 Bytes=600b=>Imcs13 =Itbs =12, Nprb =2
    f_EUTRA_OneULGrantTransmission(eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), 13, 2);
    //@siclog "Step 20" siclog@
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,728); // 728 sub frames;
      } else
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,727); // 727 sub frames;
      }
    fl_ReceiveOneMACPDU_Length(eutra_Cell1, tsc_RbId_DRB2, cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), cr_MAC_PDU_Any,55);
    f_RLC_Status_PDU_Tx (tsc_LchId_DRB2,5);
    //@siclog "Step 21" siclog@
    // Automatically taken care of
    //@siclog "Step 22" siclog@
    v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,806); // 806 sub frames;
    f_SS_SPS_PDCCH_ExplicitRelease(eutra_Cell1,
                                   cs_TimingInfo( v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                   tsc_SPS_RNTI,
                                   dci_0);
    //@siclog "Step 24" siclog@
    v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,969); // 969 sub frames;
    f_SS_ActivateSPS_Grant (eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                            cs_UL_SPSInfo (tsc_SPS_RNTI,cs_SpsAssignmentUL (cs_DciInfo_CcchDcchDtchUL_Explicit(13, 2), v_SpsConfigUL))); // NDI =0
    
    //@siclog "Steps 23 - 25" siclog@
    v_TimingP := f_EUTRA_TimingInfoAdd(v_TimingY,888); // 888 sub frames;
    v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,973); // 973 sub frames;
    
    fl_ReceiveOneMACPDU_Length_T1AndNoPDUT2(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                            cr_TimingInfo(v_TimingP.SFN.Number, v_TimingP.Subframe.Number), cr_MAC_PDU_NoSDU, 55);
    //@siclog "Step 26" siclog@
    // Automatically taken care of
    
    //@siclog "Step 27" siclog@
    if (v_EUTRA_FDD_TDD_Mode == FDD)
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,1133); // 1133 sub frames;
     } else
      {
        v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,1132); // 1132 sub frames;
      }
    fl_ReceiveOneMACPDU_Length(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo( v_Timing.SFN.Number, v_Timing.Subframe.Number), cr_MAC_PDU_NoSDU,75);
    //@siclog "Step 28" siclog@
    // Automatically taken care of
    //@siclog "Step 30" siclog@
    // Preconfig
    v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,1374); // 1374 sub frames;
    f_SS_ActivateSPS_Grant (eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                            cs_UL_SPSInfo (tsc_SPS_RNTI,cs_SpsAssignmentUL (cs_DciInfo_CcchDcchDtchUL_Explicit(13, 2), v_SpsConfigUL))); // NDI =0
    
    //@siclog "Steps 29 - 31" siclog@
    v_TimingP := f_EUTRA_TimingInfoAdd(v_TimingY,1293); // 1293 sub frames;
    v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,1378); // 1378 sub frames;
    
    fl_ReceiveOneMACPDU_Length_T1AndNoPDUT2(eutra_Cell1,tsc_RbId_DRB2, cr_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                            cr_TimingInfo(v_TimingP.SFN.Number, v_TimingP.Subframe.Number), cr_MAC_PDU_NoSDU, 55);
    //@siclog "Step 32" siclog@
    // Automatically taken care off
    
    //@siclog "Step 33" siclog@
    // SS configuration to enable reception of RRC Connection Reconfiguration Complete on SRB.
    v_Timing := f_EUTRA_TimingInfoAdd(v_TimingY,1390); // 1390 sub frames; sub frame
    // If Timing issues araise SYS.receive can be disabled
    f_SS_Config1TM_DRB_NoMACHeader_TimingInfo(eutra_Cell1,
                                              cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                              tsc_RbId_DRB2,cs_MAC_TestMode_NoHeaderManipulationDLOnly);
    v_Timing := f_EUTRA_TimingInfoAdd(v_TimingY,1419); // 1420 sub frames;
    // allows 29 sub frames for SS configuration; Selected subframe 9
    f_SendRRC_ConnectionReconfiguration_SPS_Config(eutra_Cell1,
                                                   tsc_RRC_TI_Def,
                                                   cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                                   cs_SPS_Config_UL(omit, cs_SPS_ConfigUL_Release));
    //@siclog "Step 34" siclog@
    // Grant config
    v_Timing:=f_EUTRA_TimingInfoAdd(v_TimingY,1429); // 1429 sub frames [20 TTI, Signalling Latency];
    f_EUTRA_OneULGrantTransmission(eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number), 13, 2);
    
    // to enable reception of UL MAC PDU's on DRB
    v_Timing := f_EUTRA_TimingInfoAdd(v_TimingY,1459); // 1459 sub frames;
    // allows 30 subframes for SS configuration
    // If Timing issues araise SYS.receive can be disabled
    f_SS_Config1TM_DRB_NoMACHeader_TimingInfo(eutra_Cell1,
                                              cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                              tsc_RbId_DRB2,cs_MAC_TestMode_NoHeaderManipulationDL_UL);
    //@siclog "Step 35" siclog@
    v_Timing := f_EUTRA_TimingInfoAdd(v_TimingY,1489); // 1490 sub frames; sub frame
    // app 40 ms before SPS ScheduleInterval expiry
    // 50B PDCP SDU+ 2B PDCP H + 2B RLC Header + 1 MAC SH  = 55 Bytes=600b=>Imcs13 =Itbs =12, Nprb =2
    v_EncodedRlcPdu1 := f_RLC_PDU_Encvalue (cs_RLC_AMD_1PDU(tsc_NoPoll,
                                                            int2bit(1, 10),
                                                            f_PDCP_PDU_Encvalue (cs_PDCP_PDU_LongSN(cs_PDCP_DataPdu_LongSN(tsc_B12_SQN1, crs_PDCP_SDU_L50)))));
    DRB.send (cas_DRB_COMMOM_REQ_MAC_PDU (eutra_Cell1,
                                          tsc_RbId_DRB2,
                                          cs_TimingInfo(v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                          cs_MAC_PDUList_1 (cs_MAC_PDU_NoPadding_RLCPDU_LCID( tsc_LchId_DRB2, v_EncodedRlcPdu1))));
    
    //@siclog "Step 38" siclog@
    // Preconfig
    v_Timing := f_EUTRA_TimingInfoAdd(v_TimingY,1539); // 1539 sub frames; sub frame
    // 50B PDCP SDU+ 2B PDCP H + 2B RLC Header + 1 MAC SH  = 55 Bytes=600b=>Imcs13 =Itbs =12, Nprb =2
    f_EUTRA_OneULGrantTransmission(eutra_Cell1,cs_TimingInfo(v_Timing.SFN.Number+1 ,v_Timing.Subframe.Number), 13, 2);
    //@siclog "Steps 34 - 36 - 37 - 39" siclog@
    v_Timing := f_EUTRA_TimingInfoAdd(v_TimingY,1543); // 1543 sub frames; sub frame
    // For UL transmission on C-RNTI grant
    v_TimingP := f_EUTRA_TimingInfoAdd(v_TimingY,1433); // 1433 sub frames; sub frame
    //for RRC connection Reconfiguration Complete
    if (v_EUTRA_FDD_TDD_Mode == FDD)
     {
       v_TimingQ:=f_EUTRA_TimingInfoAdd(v_TimingY,1538); // 1538 sub frames;
     } else
      {
        v_TimingQ:=f_EUTRA_TimingInfoAdd(v_TimingY,1537); // 1537 sub frames;
      }
    // for SPS Grant
    t_Watchdog.start(0.5);
    alt {
      
    //@siclog "Step 37" siclog@
    [] SYSIND.receive(car_SchedulingReq_IND (eutra_Cell1, ?))
      { repeat;}
    //@siclog "Step 34" siclog@
    [] SRB.receive(car_SRB1_RrcPdu_CheckTiming_IND(eutra_Cell1,
                                                   cr_TimingInfo(v_TimingP.SFN.Number, v_TimingP.Subframe.Number),
                                                   cr_508_RRCConnectionReconfigurationComplete(tsc_RRC_TI_Def)))
      {
        repeat;
      }
    //@siclog "Step 36" siclog@
    []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                           tsc_RbId_DRB2,
                                           cr_TimingInfo( v_TimingQ.SFN.Number, v_TimingQ.Subframe.Number),
                                           {cr_MAC_PDU_Any}))
      {
        f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 36: UE is Sending MAC PDU with SPS Grant ");
        t_Watchdog.stop;
      }
    //@siclog "Step 39" siclog@
    []DRB.receive (car_DRB_COMMON_IND_MAC (eutra_Cell1,
                                           tsc_RbId_DRB2,
                                           cr_TimingInfo( v_Timing.SFN.Number, v_Timing.Subframe.Number),
                                           {cr_MAC_PDU_NoPadding_RLCPDU_LCID(tsc_LchId_DRB2, v_EncodedRlcPdu1)}))
      {
        
        t_Watchdog.stop;
      }
    };
    
    // Deactivate SPS Grant
    f_SS_DeactivateSPS_Grant(eutra_Cell1, cs_TimingInfo_Now);
    // deactivate reception of SR's in alt step
    deactivate(v_MyDefaultVar);
    //test body ends
    f_EUTRA_TestBody_Set(false);
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    
    // to configure SS to stop report reception of SR
    f_SS_ConfigSchedulingRequestIndMode (eutra_Cell1, tsc_L1Mac_IndicationMode_Disable);
    //Configure SS for non MAC test mode in UL
    f_SS_Config1TM_DRB_NoMACHeader(eutra_Cell1, tsc_RbId_DRB2,cs_MAC_TestMode_NormalMode); //@sic R5s100272
    // configure SS for default grant allocation
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
  }; // end of 7.1.4.2
  
  group Local_TC7143_Functions {
  
  
  function f_U_Plane_SetupDataSameStartingTTI(integer p_RepetitionCnt,
                                              template (value) PDCP_SDUList_Type p_PDCP_SDUList)
    return template (value) DRB_DataPerSubframeList_DL_Type
  {
    //Function for sending all data from same TTI
    
    var integer i;
    var template (value) DRB_DataPerSubframeList_DL_Type v_DataPerSubframeList;
    for (i:=0; i<p_RepetitionCnt; i:=i+1) {
      v_DataPerSubframeList[i] := {
        SubframeOffset  := tsc_SubframeOffset0,
        HarqProcess := { Automatic := true},
        PduSduList   :=
        {
          PdcpSdu  := p_PDCP_SDUList
        }
      };
    }
    return v_DataPerSubframeList;
  }
  
  
  function fl_TC_7_1_4_3_Step1 (integer p_NumberOfSDUs1, integer p_NumberOfSDUs2, integer p_NumberOfSDUs3,
                                SystemFrameNumber_Type p_SFN,
                                 integer p_SubframeOffset) runs on EUTRA_PTC
  {
    //One ASP used to send all PDU's and PDUs on all DRBs are sent in one TTI.
    // This is necessary to guarantee that the algorithm is correct, otherwise the logical channel which DL data is sent first
    // will have more loop back data in initial stages and could result in failure of test case.
    
    //Variables for DRB subframes handling
    //var template (value) DRB_DataPerSubframeList_DL_Type v_DataPerSubframeList1, v_DataPerSubframeList2, v_DataPerSubframeList3;
   
    var EUTRA_FDD_TDD_Mode_Type  v_EUTRA_FDD_TDD_Mode:= f_EUTRA_CellInfo_GetFDD_TDD (eutra_Cell1);
    
    //To be sure that SS is ready, waiting time to start preconfigured
    
    
    
    //v_DataPerSubframeList1 := f_U_Plane_SetupDataSameStartingTTI(p_NumberOfSDUs1, cs_PDCP_SDUList_1 (cs_PDCP_SDU_L318));
    DRB.send (cas_DRB_COMMON_REQ_SubframeDataList(eutra_Cell1,
                                                  tsc_RbId_DRB2,
                                                  cs_TimingInfo(p_SFN, p_SubframeOffset),
                                                  f_BuildPDCPSDUsToBeSentInConsecutiveTTI(cs_PDCP_SDUList_1 (cs_PDCP_SDU_L318), p_NumberOfSDUs1, v_EUTRA_FDD_TDD_Mode)));
    
    //v_DataPerSubframeList2 := f_U_Plane_SetupDataSameStartingTTI(p_NumberOfSDUs2, cs_PDCP_SDUList_1 (cs_PDCP_SDU_L318));
    DRB.send (cas_DRB_COMMON_REQ_SubframeDataList(eutra_Cell1,
                                                  tsc_RbId_DRB3,
                                                  cs_TimingInfo(p_SFN, p_SubframeOffset),
                                                  f_BuildPDCPSDUsToBeSentInConsecutiveTTI(cs_PDCP_SDUList_1 (cs_PDCP_SDU_L318), p_NumberOfSDUs2, v_EUTRA_FDD_TDD_Mode)));
    
    //v_DataPerSubframeList3 := f_U_Plane_SetupDataSameStartingTTI(p_NumberOfSDUs3, cs_PDCP_SDUList_1 (cs_PDCP_SDU_L318));
    DRB.send (cas_DRB_COMMON_REQ_SubframeDataList(eutra_Cell1,
                                                  tsc_RbId_DRB4,
                                                  cs_TimingInfo(p_SFN, p_SubframeOffset),
                                                  f_BuildPDCPSDUsToBeSentInConsecutiveTTI(cs_PDCP_SDUList_1 (cs_PDCP_SDU_L318), p_NumberOfSDUs3, v_EUTRA_FDD_TDD_Mode)));
    
  }; // end of fl_TC_7_1_4_3_Step1
  

  
  function fl_TC_7_1_4_3_Step2 (integer p_Nprb, integer p_Imcs, integer p_SubframeNumber, integer p_NumberofCycles,
                                SystemFrameNumber_Type p_SFN,
                                 integer p_SubframeOffset) runs on EUTRA_PTC
  {
    //Step 2: UL Grant according to table 7.1.4.3.3.2-3
    //var SubFrameTiming_Type v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1, 150);  // 150 ms in future

    f_EUTRA_PeriodicCyclicULGrantTransmission( eutra_Cell1,
                                               cs_TimingInfo(p_SFN, p_SubframeOffset),
                                               p_Imcs, p_Nprb,  p_SubframeNumber, p_NumberofCycles);//@sic R5s100473 sic@
    /* Nprb, Itbs             Table 7.1.7.2.1-1 of 36.213
       Imcs -> Itbs      MCS index of table 8.6.1-1 of 36.213
       Grant period = p_SubframeNumber; Number of cycles = p_NumberofCycles
       |
       \--> total duration = p_SubframeNumber*p_NumberofCycles [ms]
    */
  }; // end of fl_TC_7_1_4_3_Step2
  
  
  
  function fl_TC_7_1_4_3_Step3 (integer p_DataOctetsDRB1,
                                integer p_DataOctetsDRB2,
                                integer p_DataOctetsDRB3) runs on EUTRA_PTC
  {
    //As more than one PDCP SDU can be sent by UE in one TTI, hence more than one PDCP SDU can be received in the list
    //A mechanism to know number of PDUs is implemented
    
    var integer k, l, m;
    var PDCP_SDUList_Type v_PDCP_SDU_List; // To store the number of PDCP SDUs sent by UE in one TTI
    var DRB_COMMON_IND v_DRB_COMMON_IND;
    
    timer t_Watchdog := 5.0;              // Local wait Timer
    
    t_Watchdog.start;
    k:=0;l:=0;m:=0;
    alt {
      
      [] DRB.receive (car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell1,tsc_RbId_DRB2,cr_TimingInfo_Any,cr_PDCP_SDUList_1(?))) -> value v_DRB_COMMON_IND
        {
          v_PDCP_SDU_List := v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.PdcpSdu;
          k := k+lengthof(v_PDCP_SDU_List);
          repeat;
        }
      [] DRB.receive (car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell1,tsc_RbId_DRB3,cr_TimingInfo_Any,cr_PDCP_SDUList_1(?))) -> value v_DRB_COMMON_IND
        {
          v_PDCP_SDU_List := v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.PdcpSdu;
          l := l+lengthof(v_PDCP_SDU_List);
          repeat;
        }
      [] DRB.receive (car_DRB_COMMON_IND_PDCP_SDUList (eutra_Cell1,tsc_RbId_DRB4,cr_TimingInfo_Any,cr_PDCP_SDUList_1(?))) -> value v_DRB_COMMON_IND
        {
          v_PDCP_SDU_List := v_DRB_COMMON_IND.U_Plane.SubframeData.PduSduList.PdcpSdu;
          m := m+lengthof(v_PDCP_SDU_List);
          repeat;
        }
      [] t_Watchdog.timeout
        {
          if ((0.9*int2float(p_DataOctetsDRB1)>int2float(k*320)) or (int2float(k*320)>int2float(p_DataOctetsDRB1)*1.1) or (0.9*int2float(p_DataOctetsDRB2)>int2float(l*320)) or (int2float(l*320)>int2float(p_DataOctetsDRB2)*1.1) or (0.9*int2float(p_DataOctetsDRB3)>int2float(m*320)) or (int2float(m*320)>int2float(p_DataOctetsDRB3)*1.1))
            {
              f_EUTRA_SetVerdictFailOrInconc(__FILE__, __LINE__, "Step 3: UE is not sending back all RLC SDUs ");
            }
          else
            {
              f_EUTRA_PreliminaryPass (__FILE__, __LINE__, "Step 3: Loop back SDUs received");
            }
        }
    };
    
  };// end of fl_TC_7_1_4_3_Step3
  
  }// end of Local_TC7143_Functions
  function f_TC_7_1_4_3_EUTRA() runs on EUTRA_PTC
  {
    /* L2/MAC
       7.1.4.3 : Logical channel prioritization handling
    */
    //Amount of data to be granted (bits)
    //const integer D[4] := {9144, 4584, 9144, 9144};
    //9144B -> Nprb=25;Imcs=18;
    //4584B -> Nprb=20;Imcs=13;
    const integer const_Nprb[4]:= {25, 20, 25, 25};
    const integer const_Imcs[4]:= {18, 13, 18, 18};
    
    //Number of SDUs for each run
    const integer const_N1[4]  := {13, 13, 7, 104};
    const integer const_N2[4]  := {25, 25, 50, 25};
    const integer const_N3[4]  := {50, 50, 50, 50};
    const integer const_T1[4] := {20, 20, 20, 10};
    const integer const_T2[4] := {500, 700, 500, 500}; //@sic R5-104798 sic@
    
    //R5-094660 R5-100777
    //Amount of data to compare with (octets)
    const integer const_D1[4]  := {4160, 4160, 2240, 33000};
    const integer const_D2[4]  := {8000, 8000, 10260, 8000};
    const integer const_D3[4]  := {16000, 7790, 16000, 16000};//@sic R5-104798 sic@
    var SubFrameTiming_Type v_Timing;
    
    var integer j;
    var template (value) RadioBearerList_Type v_DrbConfigList := {cs_OneDRB_ConfigAM(tsc_DRB1),
                                                              cs_OneDRB_ConfigUM(tsc_DRB2),
                                                              cs_OneDRB_ConfigUM(tsc_DRB3),
                                                              cs_OneDRB_ConfigUM(tsc_DRB4)};

    
    timer t_Watchdog := 5.0;              // Local wait Timer
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      PREAMBLE
    ///////////////////////////////////////////////////////////////////////////////////

    f_EUTRA_Init (c1);
    f_EUTRA_CellConfig_DRB_Common  (eutra_Cell1,0,3);//@sic R5s100473 sic@
    // Note the prioritized bit rate at SS is 0KBPs for all DRB's to guarntee that data is always available at UE UL.
    // All logical channels also provided same priority for the above reason.
    f_EUTRA_Preamble(eutra_Cell1,STATE2A_TESTLOOP_ModeA);
    f_EUTRA_AS_CipheringAlgorithm_Set(eea0); // set null AS ciphering algorithm
    // creates cell and performs registration
    
    //SS configured for 3 DRBs
    //Prioritized bit rates acc. to 7.1.4.3.3-1 for 3DRBs
    f_EUTRA_LoopBackActivation_State4_7143();
    
   
    ///////////////////////////////////////////////////////////////////////////////////
    //      Test Body
    //////////////////////////////////////////////////////////////////////////////////
    f_EUTRA_TestBody_Set(true);
    
    // stop UL Default Grant Transmission
    f_EUTRA_StopULGrantTransmission_PUCCH_Sync(eutra_Cell1,cs_TimingInfo_Now);
    
    // runs 1 to 4
    for (j :=0; j<= 3; j:= j+1)
      {
        //@siclog "Step 1" siclog@
        // SS sends:
        //          N1 320-octet RLC SDUs on DRB1
        //          N2 320-octet RLC SDUs on DRB2
        //          N3 320-octet RLC SDUs on DRB3
        v_Timing := f_EUTRA_GetNextSendOccasion(eutra_Cell1); //100 ms in future
        fl_TC_7_1_4_3_Step1(const_N1[j], const_N2[j], const_N3[j], v_Timing.SFN.Number,v_Timing.Subframe.Number );
        
        
        //@siclog "Step 2" siclog@
        // UL Grant of D[j] every T1=10ms for a duration of T2=500/700ms
        
        v_Timing := f_EUTRA_TimingInfoAdd (v_Timing, 150); // 150 ms later
        fl_TC_7_1_4_3_Step2(const_Nprb[j], const_Imcs[j], const_T1[j], const_T2[j]/const_T1[j],v_Timing.SFN.Number,v_Timing.Subframe.Number );//@sic R5-104798 sic@
        t_Watchdog.stop;
        
        
        
        //@siclog "Step 3" siclog@
        // RLC SDUs back to SS/check total number of octets of UL Rx
        fl_TC_7_1_4_3_Step3 (const_D1[j], const_D2[j], const_D3[j]);

        //@siclog "Step 4" siclog@
        // SS re-establish the RLC for each RB at UE
        // SS performs a RRC Connection Reconfiguration procedure including the
        // mobilityControlInfo IE triggering RLC-reestablishment.
        //@sic R5s100240 sic@

        f_EUTRA_508RRC_IntraLTE_HO_IntraCell_DSR_Transmax(eutra_Cell1,-,v_DrbConfigList); //@sic R5s100473 sic@


    };

    f_EUTRA_TestBody_Set(false);
    //test body ends
    
    ///////////////////////////////////////////////////////////////////////////////////
    //      Postamble
    //////////////////////////////////////////////////////////////////////////////////
    
    f_EUTRA_StartDefULGrantTransmission(eutra_Cell1, cs_TimingInfo_Now);
    
    // To deactivate test loop mode before RRC release
    //@sic R5-103847 Deactivate test loop and open test loop is removed sic@
    
    // Release RRC Connection and Switch off
    f_EUTRA_Postamble(eutra_Cell1, E3_TESTMODE );//@sic R5-103875 sic@
    
    
  };//end of 7.1.4.3
  
}
